Digital Logic T...

The Boolean expression A̅⋅B + A.B̅ + A.B is equivalent to

Which of the following set of components is sufficient to implement any arbitrary boolean function?

Consider a carry look-ahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is:

The minimum number of bits required to represent -12810 in 2's complement form and signed form respectively are:

If there are p input lines and q output lines for a decoder that is used to uniquely address a byte-addressable 64 KB RAM, then the minimum value of p + q is ______.

The representation of the value of a 32 bit unsigned integer X in hexadecimal number system is ABCDEF98. The representation of the value of X in octal number is

Consider the binary number in 32-bit (single precision) IEEE-754 format:

00110010001101100000000000000000

If F(P, Q) = \(\overline {P + \bar Q + PQ} \) then what is the value of F(F(M, N̅), M + N)

Which of the following is not equivalent to (a ⊕ b) if ⊕ and ⊙ denote the Exclusive OR and Exclusive NOR operation respectively?

Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 's complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is ___________

The Boolean function with the Karnaugh map is:

Consider the equation (146)_b​ + (313)​_b-2​ = (246)₈. Which of the following is the value of b?

An N-bit carry lookahead adder, where N is a multiple of 4, employs ICs 74181 (4 bit ALU) and 74182 (4 bit carry lookahead generator).

The minimum addition time using the best architecture for this adder is

The number of full and half-adders required to add 16-bit numbers is:

The following circuit compares two 2-bit binary numbers, X and Y represented by X₁X₀ and Y₁Y₀ respectively. (X₀ and Y₀ represent Least Significant Bits)

Under what condition Z will be 1?

A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only.Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.

The maximum gate delay for any output to appear in an array multiplier for multiplying two-bit numbers is:

Consider three registers R1, R2 and R3 that store numbers in IEEE-754 single precision floating point format. Assume that R1 and R2 contain the values (in hexadecimal notation) 0x42200000 and 0xC1200000, respectively.

If R3 \(= \frac{{R1}}{{R2}},\) what is the value stored in R3?

Consider an array multiplier for multiplying two n bit numbers. If each gate in the circuit has a unit delay, the total delay of the multiplier is:

The total number of Boolean functions which can be realised with four variables is:

The next state table of a 2-bit saturating up-counter is given below.

The counter is built as a synchronous sequential circuit using T flip-flops. The expressions for T₁ and T₀ are

The simultaneous equations on the Boolean variables x, y, z and w,

have the following solution for x, y, z and w, respectively:

How many pulses are needed to change the contents of a n-bit upcounter from x₁₀ to y₁₀ if x > y and x is less than 2ⁿ?

Consider the Boolean operator # with the following properties :

What is the final value stored in the linear feedback shift register if ⊕ is XOR and the input is 1101101?