Computer Organi...

The main memory of a computer has 2xy blocks while the cache has 2x blocks . If the cache uses the set-associative mapping scheme with 2 blocks per set, then block K of main memory maps to the _____set of the cache.

In a pipeline system, a task is processed in a five-segment pipeline with a clock cycle of 20 nanoseconds. A. The same task can be processed in 50 nanoseconds by the non-pipeline system. What is the speedup of the pipeline with 200 tasks?

If T₁ and T₂ are average access time of upper level memory M1 and lower level memory M2 in a 2 – level memory hierarchy and H is the hit rate in M1, then the overall average access time is given by ____, assuming that in case of a miss in M1, a block is first copied from M2 to M1 and then accessed from M1:

In a fifteen stage pipelined processor, if the branch target condition is resolved at stage 9 then find the number of stalls are predicted incorrectly?

A computer uses RAM chips of 1024 × 1 capacity.

Consider a processor in which BR 50 instruction is executed at location 1000. What is the effective address after the execution of the instruction at location 1000? Assume the address is in decimal format.

In a 32-bit processor a fully associative cache is used. The size of cache is 128 KB while that of its block is 16 bytes. If t is the size of tag in bits and i is the size of index field in bits. The value of t × i is _____ (1 word is equal to 1 byte).

If instruction X tries to modify some data before it is written by instruction (X-1), it can result in a ________ hazard.

A Hypothetical processor can support a maximum of 72 TB memory. If the system is word addressable and the size of word is 4 bytes. What is the least size of the address bus in bits?

Which of the following is an efficient method of cache updating?

In a computer with average main memory access time is 40 ns if a one-page fault(when a running program accesses a memory page that is mapped into the virtual address space, but not actually loaded into main memory) is generated for every 10⁶ memory accesses, the effective access time for the memory is _____ ns. Let the page fault service time be 20ms. (Give your answer in nearest integer)

Let a disk pack has 32 surfaces having 1 track per surface, 16 sector per track and 512 bytes per sector. Disk is rotating at 3600 RPM, what is the data transfer in KB if 1 R/W head is available over 32 surfaces?

Consider a 5 GHz (gigahertz) processor with a 4-stage pipeline and stage latencies λ₁, λ₂, λ₃ and λ₄ such that ${\lambda }_1=\frac{4{\lambda }_2}{5}=\frac{7{\lambda }_3}{4}=\frac{6{\lambda }_4}{4}$. If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is _______GHz, ignoring delays in the pipeline registers. (correct up to two decimal places)

The size of the physical address space of a processor is 2^a bytes. The word length is 2^b bytes. The capacity of cache memory is C words. The size of the block is 2^d words. For a 2^k-way set-associative cache memory, the length of the tag field in bits is.

Consider a 16-bit processor having 32 register. The two types of instruction are A and B respectively. A – type instruction has an opcode followed by two register names and B - type instruction has a opcode, a register name and a 6 – bit immediate value. Type B – instruction format has 19 distinct opcodes. What is the maximum number of distinct A-type opcodes? 

A processor has 72 distinct instruction and 28 general purpose registers. A 16-bit instruction word has an opcode, one register operands and an immediate operand. The maximum decimal value possible of the immediate operand if operand is in 2’s complement is _____.

Consider a processor which generates 32-bit address. A system uses write back policy in 256 KB direct mapped cache. It consists of multiple blocks with each block size as 32 bytes. The cache controller maintains the tag information for each cache block comprising of 1 modified bit, 1 replacement bit and 1 valid bit. The total size of memory needed at the cache controller to store meta-data for the cache is _____ KB?

A 64 Gb DRAM chip is organized as 8 G × 8 memory externally and as 256 K × 256 K square array internally. Refreshing each row takes 20 ns. Each row must be refreshed at least once every 0.05 s. The percentage (rounded to the closet integer) of the time available for performing the memory read/write operations in the main memory unit is ________. 

Consider a system consisting of thirty-two bits virtual address, page size is 16 KB and a 512 lines of translation look-aside buffer organized into 64 sets each. TLB is 8 -way set associative. What is the minimum length of TLB tag in bits (TLB does not store any process ID)?

Consider a system which is byte-addressable. Let a and b be two unsigned numbers of 16 bit each. If ROM stores the result of the multiplication of such numbers, then what is the required size of ROM in GB)?

In a word-addressable processor, a cache block is 32 words. A word size is 4 bytes. The main memory has a latency of 48 nanoseconds with a bandwidth of 8 GB/s. The time requires to fetch the entire cache block is _____.

The size of the data count register of a DMA controller is 24 bits. The processor needs to transfer a file of 4 GB from disk to memory. The memory is word addressable and size of a word is 2 bytes. What is the minimum number of times the DMA controller need to get the control of the system bus from the processor to transfer the file from the hard disk to main memory?

In a computer, a memory unit is of size 256 KW where w stands for word. Word size is 32 bits. The instruction has four parts: addressing mode, operation code, register code and address part. An addressing mode part is used to specify one of two-addressing mode (direct or indirect). Register code part is used to specify one of the 64 registers. How many bits are there in addressing mode part, opcode part, register code part, and the address part?