Computer Organi...

Consider a direct mapping implementation where the main memory size is 32GB, the block size is 8 KB and the number of tag bits is 10. What is the cache size (in MB) in the given implementation?

Consider a fully associative cache with 8 cache blocks and the following sequence of memory block request (5, 4, 26, 8, 20, 7, 26, 8, 17, 36, 46, 23, 8, 4, 17, 26, 9). If LRU replacement policy is used then which cache block will have memory block 17?

Which of the following statement is/are not correct about addressing modes?

The following program is stored in the memory unit of the basic computer. Give the content of accumulator register in hexadecimal after the execution of the program.

Location	Instruction
010	CLA
011	ADD 016
012	BUN 014
013	HLT
014	AND 017
015	BUN 013
016	C1A5
017	93C6

 

Consider a 5- stage instruction pipeline where the delay of S4 is half to that of S1. S2 has a half delay to S3. S1 is having a delay of 10 ns. S5 and S3 have the same delay as S1 . What will be the speed up achieved in this?

A computer uses a memory unit of 512 K words of 32 bits each. A binary instruction code is stored in one word of the memory. The instruction has four parts: an addressing mode field to specify one of the two-addressing mode (direct and indirect), an operation code, a register code part to specify one of the 256 registers and an address part. How many bits are there in addressing mode part, opcode part, register code part and the address part?

Consider a cache, in which the block has 512 bytes. The main memory has a latency of 32 ns and a bandwidth 4 GB/s. The time required to fetch the entire cache line is _____ ns.

If tag comparator size required for direct, fully associative and set- associative mapping are x,y and z respectively, then which of the following is correct?

Consider a paging system with page table stored in memory and with additional associative registers. If 75 percent of all page table reference are found in the associative register, and a memory access takes 240 ns, what is the effective memory reference time? Assume the time taken to find a page in associative register is 0.

Consider the Reduced Instruction Set Computer (RISC) characteristics mentioned in options

Choose the correct characteristics from the options given below:

A processor that has carry, and overflow flags bits as part of its program status word(PSW) addition of the following in 2’s complement number 0110 1001 and 0100 1101. After the execution of this addition operation, the status of the carry and overflow respectively will be

A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider the following four physical addresses represented in hexadecimal notation.

A1 = 0x42C8A4, A2 = 0x546888, A3 = 0x6A289C, A4 = 0x5E4880

Which one of the following is TRUE?

In 8-way set-associative cache memory, the capacity of the cache memory unit 512 KB. It is built using a block size of 16 words. The size of the physical address space is 4096 MB with a word length of 32 bits. The number of bits for the tag field is _____

A CPU has 6 stages pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline followed by instruction decode, calculate effective address, fetch operands, execute instruction and write back. A conditional branch instruction computes the target address and evaluates the condition in the fourth stage of the pipeline. The processor stops fetching new instructions following a condition branch until the branch outcome is known. A program executes 10¹⁰ instructions out of which 30% are conditional branch. If each instruction takes 2 cycle to complete on average, then total execution time of the program in seconds

Consider a disk space pack with the following specifications 16 surfaces, 128 tracks per surface, 256 sectors per tracks and 512 bytes per sector.

a) In this, if format overhead is 64 bytes/sector, then what is formatted disk space?

b) If disk is rotating at 2400 rotations per minute, then what is data transfer rate?

The read access time and the hit ratios for Instruction cache (I - cache), Data cache (D-cache), L₂ cache in a memory hierarchy given below:

Cache	Read access time	Hit ratios
I-cache	2	0.9
D-cache	1	0.9
L2-cache	5	0.8

 

In an execution, 80% of memory reads instructions are for instruction fetch and 20% of memory reads are for data fetch. The read access time of the main memory is 100 nanoseconds(ns). The cache uses referred word-first policy and write-back policy. The dirty bit is always 0 for all blocks in the caches and caches are directly mapped. The average read access time _____ ns. (correct up to 2 decimal places)

Consider a pipeline processor with 5 stages S1 to S5. We want to execute the following loops: while(i ≤ 1) {I1, I2, I3, I4} where i = 0. Time(ns) taken by the instruction I1 to I4 for stages S1 to S5 are given below:

	S1	S2	S3	S4	S5
I1	1	1	2	1	1
I2	1	2	1	1	1
I3	1	2	2	1	1
I4	2	1	2	1	1

 

The output of I4 will be available after

Which of the above statements is/are FALSE?

A certain processor deploys a single-level cache. The cache block size is 16 words and the word size is 4 bytes. The memory system uses a 100-MHz clock. To service a cache miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 5 cycles to fetch all the sixteen words of the block, and finally transmits the words of the requested block at the rate of 2 cycle per word. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is ________× 10⁷ bytes/sec.

A hard disk has 32 sectors/ track, 10 platters each with 2 recording surface and 1000 cylinders. The address of a sector is given as where c is cylinder no., h is for surface no., s is for sector no. Thus the 0^th sector is addressed as <0, 0, 0>, 1^st sector as <0, 0, 1> and so on.

Then the address <200, 8, 20> corresponds to which sector no.?

Consider a 32-bit processor which supports 70 instructions. Each instruction is 32 bit long and has 4 fields namely opcode, two register identifiers and an immediate operand of unsigned integer type. Maximum value of the immediate operand that can be supported by the processor is 8191. How many maximum registers the processor has?

Consider a system with 2 – level cache, at 0.6 hit ratio in level 1 memory. The L1 memory is 4 times faster than L2. The average access time is increased by 40% from 50 ns. What is the percentage of change in the hit ratio?

NOTE:
Choose the nearest answer

Consider a hypothetical system in which the data count register of a DMA controller is 32 bits. The processor needs to transfer a file of 31245 GB from a disk to main memory. The minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _________ (system is  byte addressable).