Digital Logic Test 3

Result

Digital Logic Test 3

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Question 1
1 / -0

If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is ______.

A
1034-1034

B
10344-10341

C
10347-10346

D
10349-10342

Solution

Concept:
A decoder with k input lines has 2^k output lines.
Calculation:
The memory is byte addressable. So 1 KB = 2¹⁰ B.
10 × 2¹⁰ decoder.
So, the number of input lines (m) = 10
Number of output lines (n) = 2^m = 2¹⁰ = 1024
Hence, (m + n) = 10 + 1024 = 1034
Question 2
1 / -0

Consider the addition of two binary X and Y boolean variables, results in a SUM and a CARRY output.
Find the correct boolean expressions for SUM and CARRY outputs.

A
SUM = X⋅Y̅ + X̅.Y

B
SUM \( = X \cdot Y + \;\overline {XY} \)

C
CARRY = X + Y

D
CARRY = X⋅Y
Solution
Concept:
In binary arithmetic:
- 0 + 0 = 0 (No carry)
- 0 + 1 = 1 (No carry)
- 1 + 0 = 1 (No carry)
- 1 + 1 = 0 (Carry = 1)
It’s corresponding truth table is drawn below:
X
Y
SUM (EX-OR)
CARRY(AND)
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Using K-map for the above truth table, we can get the expression for sum & carry. This is as shown:
SUM = X⋅Y̅ + X̅.Y & Carry = X.Y
Hence Option (1) and 4 are correct.
Question 3
1 / -0

If the minimum number of 8 × 1 MUX needed to implement 1024 × 1 MUX is x and the number of levels is y then x × y is equal to _____.

A
588-588

B
5884-5881

C
5887-5886

D
5889-5882

Solution

L ≥ log₈1024
where L is number of levels
L = 4
1st level \(= \frac{{1024}}{8} = 128\)
2nd level \(\; = \frac{128}{8} = 16\)
3rd level \(= \frac{16}{8} = 2\)
4th level \(= \frac{2}{8} = 0.25= 1 \ MUX\)
Total number of 8 × 1 MUX = x =128 + 16 + 2 + 1 = 147
Total number of levels = y = 4
∴ x × y = 147 × 4 = 588
Question 4
1 / -0

Assume that for a full adder implementation, the delay for sum and carry generation are 5 nsec and 3 nsec respectively. The worst-case delay of a 8-bit ripple carry adder will be:

A
26-26

B
264-261

C
267-266

D
269-262

Solution

Formula:
The total time taken by the for ‘n’ bit ripple carry adder is
Td = (n – 1) tc + Maximum(tc, ts)
tc = delay for carry through a single flip flop.
ts = delay for sum
T_d = total delay
Data:
From this, Maximum(tc, ts) = ts = 5 ns
Tc = 3 ns.
n = 8
Calculation:
Td = (n – 1) tc + Maximum(tc, ts)
Td = (8 – 1)×3 + 5
∴ Td = 26 ns
The worst-case delay of a 8-bit ripple carry adder will b 26 ns