Computer Organization and Architecture Test 1

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Computer Organization and Architecture Test 1

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Question 1
1 / -0

At run time, which of the following addressing modes is suitable for program relocation?

A
Indirect addressing mode

B
Immediate addressing mode

C
Base addressing mode

D
stack addressing mode

Solution

Concept:
In relative addressing mode, the operand filed contains a relative address which is called offset and in base addressing mode the operand field contains the offset hence it is suitable for program relocation
Effective address = program counter + offset
Question 2
1 / -0

Which of the following is/are TRUE about addressing mode in below given statement?
I. int *p corresponds to Indexed addressing mode
II. for (i = 0; i <; n; i++) corresponds to Indirect address mode.

A
Only I

B
Only II

C
Neither I nor II

D
Both I and II

Solution

Statement I: False
int *p → p is a pointer of type integer, which will store the address an integer variable.
Therefore, int *p corresponds to indirect addressing mode
Statement II: False
for (i = 0; i <; n; i++) corresponds to auto increment addressing mode.
Question 3
1 / -0

A stack organized computer has which of the following instructions?

A
zero-address

B
one-address

C
two-address

D
three-address
Solution
- A stack-organized computer does not use an address field for the instructions ADD and MUL; The PUSH and POP instructions, however, need an address field to specify the operand that communicates with the stack
- The following program shows how X = (A + B) will be written for a stack organized computer; (TOS stands for top of stack)
PUSH A TOS <- A
PUSH B TOS <- B
ADD TOS <- (A + B)
POP X M[X] <-TOS
To evaluate arithmetic expressions in a stack computer, it is necessary to convert the expression into reverse Polish notation. The name "zero-address" is given to this type of computer because of the absence of an address field in the computational instructions.
Question 4
1 / -0

Consider a processor uses 3-byte instruction format, processor has 1024 register and support 2 – address instruction. If processor support 64 1 – address instruction, then number of 2 – address instruction is _____.

A
7

B
8

C
15

D
16

Solution

Instruction format = 3 byte = 24 bit
Total = 2²⁴
1 – address = 64 × 2¹⁰
2 – address = t × 2¹⁰ × 2¹⁰
1 address + 2 address ≤ 2²⁴
64 × 2¹⁰ + t × 2¹⁰ × 2¹⁰ ≤ 2²⁴
1 + t × 2⁴ ≤ 2⁸
t ≤ 15.93
t = 15
Question 5
1 / -0

A CPU has 35 registers and uses 12 addressing modes. RAM is 32K × 48. What is the maximum size of the op-code field if the instruction has a register operand and a memory address operand?

A
19 bits

B
23 bits

C
26 bits

D
30 bits

Solution

Data:
number of registers = 35
addessing mode = 12
RAM size = 32K × 48 = 215 × 48
Formula:
Memory Capacity is of the form = 2m × n
Address lines required = m
Instrcution size = Data Lines = n
number of bits = ⌈log₂ m⌉
number of register or number addressing modes
Calculation:
Instrcution size = Data Lines = 48 bits
Address lines required = 15 bits
number of bits for a addressing mode = ⌈log2 12⌉ = 4
number of bits for a register field = ⌈log2 35⌉ = 6
Addressing Mode
op-code field
Register
Memory Address field
4 bits
x bits
6 bits
15 bits

4 + x + 6 + 15 = 48
∴ x = 23
op-code field = 23 bits
Question 6
1 / -0

Consider an instruction consisting of operation code (opcode), source register and destination identifier along with immediate operand filed. If the 32-bit processor is having 18 registers and instruction set is of size 50. What is the maximum value that an immediate operand can hold if the number system followed by processor is unsigned?

A
65535-65535

B
655354-655351

C
655357-655356

D
655359-655352

Solution

Data:
Number of registers = 18
Number of instructions = 50
Formula:
Number of bits = ⌈ log₂N ⌉
Calculation:
Number of bits to address register = ⌈ log₂ 18 ⌉ = 5
Opcode size = ⌈ log₂ 50 ⌉ = 6 bits
source register = destination register = 6 bits
Opcode
Source Register
Destination register
Immediate
6 bits
5 bits
5 bits
x bits

Total bits per instruction = 6 + 5 + 5 + x = 32 bits
∴ number of bits in immediate operand field = x = 16
Maximum value in unsigned number = 2ⁿ – 1 = 65535
Question 7
1 / -0

Consider a processor with 28 registers and an instruction set of size 35. Each instruction has four distinct fields, namely, opcode, one source register identifiers, one destination register identifier, and a sixteen-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has 2000 instructions, the amount of memory consumed by the program text is ______ KB. (1 K = 10³)

A
8-8

B
84-81

C
87-86

D
89-82

Solution

Data:
Number of registers = 28
Number of instructions = 35
Formula:
Number of bits =⌈ log₂N ⌉
Calculation:
Number of bits to address register = ⌈ log₂ 28 ⌉ = 5
Opcode size = ⌈ log₂ 35 ⌉ = 6 bits
source register = destination register = 5 bits
Opcode
Source Register
Destination register
Immediate
6 bits
5 bits
5 bits
16 bits

Total bits per instruction = 6 + 5 + 5 + 16 = 32 bits
In terms of bytes= \(\frac{{32}}{8}\)= 4 bytes
Total instructions = 2000
Total size = 2000 × 4 = 8000 bytes = 8 KB
Question 8
1 / -0

In 8085 microprocessors, what is the output of following program?
LDA 8000H
MVI B, 30H
ADD B
STA 8001H

A
Read a number from input port and store it in memory

B
Read a number from input device with address 8000H and store it in memory at location 8001H

C
Read a number from memory at location 8000H and store it in memory location 8001H

D
Load A with data from input device with address 8000H and display it on the output device with address 8001H

Solution

LDA 8000H – transfers the data from memory location 8000H to Accumulator
MVI B, 30H – moves the value 30H to Register B
ADD B – Adds the value of Register B (30H) to the data in Accumulator which stores data from location 8000H. This instruction basically increments the value as 8000H by 30H.
STA 8001H – stores the content of Accumulator to memory location 8001H
Therefore, the above code reads a number from memory at location 8000H and stores in memory location 8001H after incrementing it by 30H.
Question 9
1 / -0

Assume an instruction set that uses a fixed 20-bit instruction length. Operand specifiers are 6 bits in length. There are K two-operand instructions and no zero-operand instructions. What is the maximum number of one-operand instructions that can be supported?

A
214 – 26 K

B
214 K

C
214 + 26 K

D
2²6 K

Solution

Data:
Instruction length = 20 bits
Total address possible = 2²⁰
Operand specifiers = 6 bits
0 – address = 0
1 – address = y × 2⁶
2 – address = K × 26 × 26= 212 K
Formula:
0 – address + 1 – address + 2 – address ≤ Total Address
Calculation:
0 + y× 2⁶ + 212 K ≤ 220
y ≤ 2¹⁴ – 2⁶ K
y_max = 214 – 26 K
∴ option 1 is correct

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Addressing Mode	op-code field	Register	Memory Address field
4 bits	x bits	6 bits	15 bits

Opcode	Source Register	Destination register	Immediate
6 bits	5 bits	5 bits	x bits

Computer Organization and Architecture Test 1

Result

Computer Organization and Architecture Test 1

Score

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Rank

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SHARING IS CARING

Question 1

Indirect addressing mode

Immediate addressing mode

Base addressing mode

stack addressing mode

Solution

Question 2

Only I

Only II

Neither I nor II

Both I and II

Solution

Question 3

zero-address

one-address

two-address

three-address

Solution

Question 4

7

8

15

16

Solution

Question 5

19 bits

23 bits

26 bits

30 bits

Solution

Question 6

65535-65535

655354-655351

655357-655356

655359-655352

Solution

Question 7

8-8

84-81

87-86

89-82

Solution

Question 8

Read a number from input port and store it in memory

Read a number from input device with address 8000H and store it in memory at location 8001H

Read a number from memory at location 8000H and store it in memory location 8001H

Load A with data from input device with address 8000H and display it on the output device with address 8001H

Solution

Question 9

214 – 26 K

214 K

214 + 26 K

226 K

Solution

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2²6 K