Computer Organi...

One instruction tries to write an operand before it is written by previous instruction. This may lead to a dependency called

We have 10-stage pipeline, where the branch target conditions are resolved at stage 5. How may stalls are there for an incorrectly predicted branch?

Consider a four-stage pipeline with stage latencies 3 ns, 4 ns, 7ns, and 5 ns respectively. If registers are placed between the stages with a latency of 1 ns. What is the clock frequency of the given processor in MHz?

In a 4- stage pipeline processor. The number of cycles needed by the five instructions N₁, N₂, N₃, N₄ and N₅

What is the number of cycles needed to execute the following loop?

for(int j = 0; j < 1; j++)

{

N₁;

N₂;

N₃;

N₄;

N₅;

}

A pipelined processor executing with a constant clock rate has 5 stages. The five stages are Fetch, Decode, Execute, Memory Access and Write Back.  Latency of the stages are 100, 80, 120, 150 and 140 nanoseconds respectively. If a register which has a delay of 10 ns is used between the different stages of the pipelined processor. The time taken to execute 2001 instruction for a pipelined processor is _____ microseconds.

Consider the following processor (ns stands for nanoseconds). Assume that the pipeline registers have zero latency.

P1: Four-stage pipeline with stage latencies 2 ns, 3 ns, 3 ns, 2 ns.

P2: Four-stage pipeline with stage latencies 2 ns, 2.5 ns, 2.5 ns, 2.5 ns.

P3: Five-stage pipeline with stage latencies 1 ns, 2 ns, 3 ns, 1.2 ns, 2 ns

P4: Five-stage pipeline with stage latencies 1.5 ns, 1.5 ns, 2 ns, 1 ns, 2 ns

Which processor has the lowest peak clock frequency?

Consider a 5-stage pipeline are 3, 5, 8, 2 and 4 nanoseconds in which 1^st stage is with 3 nanosecond, 2^nd stage is with 5 nano seconds and so on. The third stage is replaced with a functionally equivalent design involving two stages with 5 and 4 nanoseconds respectively. The throughput increase of the pipeline is _______ percent.

In a non-pipelined processor, to execute one instruction 5 cycles are needed. The clock speed of non-pipelined processor is 4 GHz. If same processor is changed to pipelined processor having 6 stages. The clock rate of pipelined processor is changed to 3 GHz. What is the speedup achieved in this pipelined processor?(Assume no stalls in pipelined processor)

Consider a pipeline CPU with a single arithmetic logic unit (ALU)

Which one of the statements may cause a hazard?

Consider a 5-stage pipeline with stage delays 8 ns, 2 ns, 12 ns, 15 ns, 9 ns. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2.5 ns. The speedup factor achieved by pipeline implementation over non – pipeline implementation is 1.05. Average execution time for non-pipeline implementation is 1911 ns. Find the number of instructions.