Digital Electronics Test 1

Concept:

A quadratic equation with factor α and β can be written as:

x² – (α + β) x + (αβ) = 0

Application:

Given the quadratic equation:

x² – 11x + 22 = 0         ---(1)

Also, the solutions to the given quadratic equation are 3 and 6.

∴ We can write the quadratic equation as:

x² – (6 + 3) x + (6 × 3) = 0       ---(2)

Comparing the two-equations, we can write:

(6)_b + (3)_b = (11)_b i.e. for some base ‘b’, this equation must hold true.

Converting both the RHS and LHS to their respective decimal equivalent, we can write:

(6 × b⁰) + (3 × b⁰) = (1 × b¹ + 1 × b⁰)

6 + 3 = b + 1

b = 8

∴ The base of the number is 8 that satisfies the above quadratic equation.

Concept:

Δt = NT_c

Where,

Δt is the total delay required

N is number of flip flops

T_c is the clock time cycle

Calculation:

Given that,

Δt = 0.32 ms

Clock frequency, f_c = 1.25 MHz

\({T_c} = \frac{1}{{{f_c}}} = \frac{1}{{1.25\; \times \;{{10}^6}}} = 0.8\;\mu sec\) 

\(N = \frac{{{\rm{\Delta }}t}}{{{T_c}}} = \frac{{0.32\; \times \;{{10}^{ - 3}}}}{{0.8\; \times\; {{10}^{ - 6}}}} = 400\)

Here, (0, 1, 1) gives the output X = 1

The numbers that differ by only a single bit from their preceding number are represented using the Gray code. Here is why Gray code is used:

• Gray code ensures that only one bit changes at a time, reducing the chance of errors during transitions.
• This property is important in systems where changes from one state to another should be smooth and error-free.
• Commonly used in rotary encoders and digital communication to ensure data integrity.

The AND gate follows both the commutative and associative laws. Here's why:

• The commutative law means that the order of inputs does not change the output. For an AND gate: A & B = B & A.
• The associative law allows grouping of inputs without affecting the result. For an AND gate: (A & B) & C = A & (B & C).

Therefore, the AND gate is the correct option as it satisfies both laws.

A latch is a type of digital storage device used to store one bit of data. It is a fundamental building block in digital electronics.

• Latches are commonly used in circuits to maintain a state until changed by an input signal.
• They differ from flip-flops, which are more complex and triggered by clock signals.
• A D-type latch holds a value with a single data input and a control signal.

Latches play a crucial role in memory devices and data storage operations in computing systems.

We know that,

V_in T₁ = V_ref T₂

⇒ 120 × 10^-3 × 50 × 10^-3 = 100 × 10^-3 × T₂

⇒ T₂ = 60 ms

Concept:

1’s complement representation of a binary number is obtained by toggling all the bits, i.e. replacing 1 with 0, and 0 with 1.

2’s complement representation of a binary number is obtained by adding 1 to the 1’s complement representation.

Application:

(127)₁₀ = (01111111)₂

1’s complement representation will be:

1’s complement = 10000000

Number of 1’s is the 1’s complement is, n = 1

Now, the two (2’s) complement representation will be:

2’s complement = 10000000 + 1

= 10000001

Number of 1’s in 2’s complement is, m = 2

∴ The required ratio is m : n = 2 : 1

\(\begin{array}{l}\left( {\bar A + \bar B} \right)\left[ {\overline {A\left( {B + C} \right)} } \right] + A\left( {\bar B + \bar C} \right)\\= \left( {\bar A + \bar B} \right)\left[ {\bar A + \left( {\overline {B + C} } \right)} \right] + A\left( {\bar B + \bar C} \right)\end{array}\)

\(\begin{array}{l}= \left( {\bar A + \bar B} \right)\left[ {\bar A + \bar B\bar C} \right] + A\bar B + A\bar C\\= \bar A + \bar A\bar B\bar C + \bar A\bar B + \bar B\bar C + A\bar B + A\bar C\end{array}\)

\(\begin{array}{l}= \bar A\left( {1 + \bar B\bar C + \bar A\bar B} \right) + \bar B\bar C + A\bar B + A\bar C\\= \bar A + \bar B\bar C + A\bar B + A\bar C\end{array}\)

\(\begin{array}{l}= \bar A + A\bar B + A\bar C\\= \bar A + A\left( {\bar B + \bar C} \right)\end{array}\)

\(\begin{array}{l}= \bar A + \bar B + \bar C\\= \overline {ABC} \end{array}\)

The given Boolean expression represents NAND gate.

Given, contents A = AA H

CPI 99 H:

Compares the data 99 H with contents of A, the compression is made by subtracting 99 H from contents of A (i.e. AA H). the contents of A remains unaffected but status of result is reflected by Flags.

\(\begin{array}{*{20}{c}}{A;}&{10101010}\\{99\;H;}&{\begin{array}{*{20}{c}}{\underline {10011001} }\\{000010001}\end{array}}\end{array}\) 

After comparison both zero flag and carry flag are reset.

XRA A:

The instruction XRA A performs ExOR operation on contents of A with contents of A only and stores the result in A. The instruction clears the contents of A. So, the zero flag is set by the instruction.

LXI B, 0007H:

Loads BC pair with 16-bit data 0007 H. So, contents of BC pair become 0007 H.

LOOP: DCX B:

Decrements the contents of BC pair by one.

JNZ LOOP:

Jumps the execution of a program to LOOP if zero flag is not set.

In the above program zero flag is set when XRA A is executed and the status of zero flag remains unaffected by DCX B instruction as it does not affect the flags. So, the execution comes out of LOOP during first instance itself as Z flag is already set. So, the loop runs only once.

The truth table is shown for the given information.

Thus, we require 3 NAND gates for an OR gate while 5 NAND gates for an EX-NOR gate.

Hence, the output y is equivalent to output of an AND gate having two inputs A and 6. Thus, an AND gate is equivalent to a series switching circuit.

Step size \(= \frac{{2mA}}{{{2^8} - 1}} = \frac{{2mA}}{{255}}\)

= 7.84 μA.

10000000 = 128₁₀

Ideal output = 128 × 7.84 μA

= 1004 μA

Error = ± 0.5% × 2mA

= ± 10 μA

Range of output = 1004μA ± 10 μA

Maximum possible output : 1014 μA

Observations:

• The output is 1 when either A is 1 and B is 0 or when A is 0 and B is 1.
• The output is 0 when both A and B are 1.

This truth table corresponds to the XOR (Exclusive OR) gate.

XOR Gate:

• The XOR gate outputs 1 when the inputs are different, and 0 when the inputs are the same.

Given the truth table:

• When A=1 and B=0, output f=1
• When A=0 and B=1, output f=1
• When A=1 and B=1, output f=0

Conclusion:

The logic gate represented by the above truth table is the XOR gate.

Thus, the gate can be either an EX-NOR or a NOR gate.

The truth table for the given condition is shown below:

Thus, Y = AB + BC + CA which can be implemented using 3 AND gates and 1 OR gate (total 4 basic gates).

A₁₃, A₁₄, A₁₅ are chip select lines. To select chip, the output of OR gate should be zero

⇒ A₁₃ = A₁₄ = A₁₅ = 0

A₀ to A₁₂ can be anything.

Chip select lines				Register select lines												Range
A15	A14	A13	A12	A11	A10	A9	A8	A7	A6	A5	A4	A3	A2	A1	A0	Address
0 0	0 0	0 0	0 0	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0 1	0000 H 1FFF H