Computer Science Test

Question 1
2 / -0.66

If transaction T1 reads a change made by transaction T2, then T1 commits only after T2 commits. This property of a transaction schedule is known as:

A
Strict

B
Serializable

C
Recoverable

D
Cascadeless

Question 2
2 / -0.66

Given the following binary number in 32-bit (single precision) IEEE-754 format:

11000100010101100000000000000000

The decimal value closest to this floating-point number is

A
-866

B
856

C
866

D
-856

Question 3
2 / -0.66

What shall be the 2’s complement represented of -24 in a 16 bit computer?

A
1111 1111 1110 1011

B
1111 1111 1110 1001

C
1111 1111 1110 0111

D
1111 1111 1110 1000

Question 4
2 / -0.66

Consider two relations P and Q. Let M is a primary key of relation Q and N is the foreign key of relation P. N refers to M. Let A be a set of all values of column M and B be a set of all non-NULL values of column N. Which of the following statement is correct ? (Suppose A and B holds in all instances of P and Q)

A
B ⊆ A

B
B ⊂ A

C
A ⊆ B

D
A ⊄ B and B ⊄ A

Question 5
2 / -0.66

A
only a true

B
only a, b true

C
only b,c true

D
All a, b, c are true

Question 6
2 / -0.66

Consider the following recursive C function that takes two arguments

unsigned int rer (unsigned int n, unsigned int r) {

if (n > 0) return (n%r + rer (n/r, r));

else return 0;

}

What is the return value of the function rer when it is called as rer (513, 2)?

A
9

B
8

C
5

D
2

Question 7
2 / -0.66

Consider 10 KBPS IO device interfaced to 32–bit CPU in cycle stealing mode of DMA. Whenever 16 word data is available in the buffer, it is transferred to main memory. Machine cycle time is 100 micro seconds . How much % of CPU time is consumed in this operation?

A
22

B
23

C
24

D
25

Question 8
2 / -0.66

Consider the following statements:

S₁ : ∀x P(x) ∨ ∀xQ(x) and ∀x(P(x) ∨ Q(x)) are not logically equivalent.

S₂ : ∃x P(x) ∧ ∃x Q(x) and ∃x (P(x) ∧ Q(x)) are not logically equivalent

Which of the following statements is/are correct?

A
Only S₁

B
Only S₂

C
Both S₁ and S₂

D
Neither S₁ and S₂

Question 9
2 / -0.66

Directions For Questions

Consider a pipelined processor operating at 2 GHZ with 5 stages, Instruction fetch (IF), Instruction decode (ID), Execute (EX), Memory access (MEM), and write back (WB). Each stage of the pipeline, except the EX stage, takes one cycle. The EX takes one cycle for ADD and SUB, three cycles for MUL, two cycles for DIV Instruction.

...view full instructions

Consider the following instructions:

l₁ : ADD R₁, R₂, R₃ ; R₁ ← R₂ + R₃

l₂ : SUB R₃, R2, R1 ; R3 ← R2 - R1

I₃ : MUL R₄, R₁, R₂ ; R4 ← R5 * R2

l4 : DIV R₃, R₄, R₃ ; R3 ← R4 / R₃

Find, the number of true data dependences in the above code and the execution time using operand forwarding technique respectively is______.

A
3, 5.5 ns

B
5, 5.0 ns

C
3, 4.2 ns

D
2, 3.0 ns

Question 10
2 / -0.66

Consider the following 6 concurrent processes where the semaphore is initialized to zero.
A: down(s); cs; up (s);
B: down(s); cs; up (s);
C: down (s); cs; up(s);
D: up(s); cs; down(s);
E: up(s); cs; down(s);
F: up(s); cs;down(s);

What is the maximum value of s?

A
3

B
4

C
5

D
6

Submit Test

Computer Scienc...

Question 1

Strict

Serializable

Recoverable

Cascadeless

Question 2

-866

856

866

-856

Question 3

1111 1111 1110 1011

1111 1111 1110 1001

1111 1111 1110 0111

1111 1111 1110 1000

Question 4

B ⊆ A

B ⊂ A

A ⊆ B

A ⊄ B and B ⊄ A

Question 5

only a true

only a, b true

only b,c true

All a, b, c are true

Question 6

9

8

5

2

Question 7

22

23

24

25

Question 8

Only S1

Only S2

Both S1 and S2

Neither S1 and S2

Question 9

3, 5.5 ns

5, 5.0 ns

3, 4.2 ns

2, 3.0 ns

Question 10

3

4

5

6

User

Question Analysis

Results Announcement on: coming Monday

Stay Tuned: We’ll update you on your result via email or SMS.

Only S₁

Only S₂

Both S₁ and S₂

Neither S₁ and S₂