Computer Organization and Architecture Test 1

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Computer Organization and Architecture Test 1

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Question 1
2 / -0.33

The main memory of a computer has 2xy blocks while the cache has 2x blocks . If the cache uses the set-associative mapping scheme with 2 blocks per set, then block K of main memory maps to the _____set of the cache.

A
(k mod y)

B
(k mod xy)

C
(k mod x)

D
(k mod 2xy)

Solution

Data:
Main Memory = 2xy blocks
block of Main Memory = K
Cache = 2x blocks
block per set = 2
Formula:
mapped set = (number of sets in a cache) mod (block of main memory)
\(number\ of\ sets = \frac{number\ of\ cache\ blocks}{blocks\ per\ set}\)
Solution:
\(number\ of\ sets = \frac{2x}{2} = x\)
mapped set = K mod x
Question 2
2 / -0.33

In a pipeline system, a task is processed in a five-segment pipeline with a clock cycle of 20 nanoseconds. A. The same task can be processed in 50 nanoseconds by the non-pipeline system. What is the speedup of the pipeline with 200 tasks?

A
2.45-2.46

B
2.454-2.461

C
2.457-2.466

D
2.459-2.462

Solution

n = 200 tasks,
For a pipelined system,
number of segments, k = 5
clock cycle of each segment = tp = 20 ns
For a non-pipelines system,
time to process a task, t_n = 50 ns
Calculation
\(Speed \; up = \frac{n \times t_n}{(n + k - 1)t_p}\)
\(Speed \; up = \frac{200 \times 50}{(200 + 5 - 1)20}\)
∴ speed up = 2.4509
Question 3
2 / -0.33

If T₁ and T₂ are average access time of upper level memory M1 and lower level memory M2 in a 2 – level memory hierarchy and H is the hit rate in M1, then the overall average access time is given by ____, assuming that in case of a miss in M1, a block is first copied from M2 to M1 and then accessed from M1:

A
T₁ + (1 – H) × T₂

B
(1 – H) × T₁ + T₂

C
(T₁ + T₂) (1 – H)

D
T1 + T₂ (1 + H)

Solution

Concept:
First a page is accesses in upper level memory, if it is present there then it is called as hit. But if page is not find in upper level memory, then it is called as miss, for this page is first copied from lower memory to upper level memory. During miss, it involves first access time for upper level memory then access time for lower level memory.
Explanation:
T₁ is the memory access time for memory M₁
T₂ is the memory access time for memory M₂.
H is the hit rate in M₁.
So, 1- H is the hit rate in M₂.
In serial manner:
Average access time will be = H T₁ + (1 – H).(T₁ + T₂) = T₁ + (1– H)T₂
Because first page is accesses in memory M₁ and it takes T₁ time. If page not found there, then it will be
Accessed in M₂ and takes T₂ time with miss rate (1 – H).
Question 4
2 / -0.33

In a fifteen stage pipelined processor, if the branch target condition is resolved at stage 9 then find the number of stalls are predicted incorrectly?

A
8-8

B
84-81

C
87-86

D
89-82

Solution

Concept:
The branch condition guesses the outcome of conditional operations and then find the next result. The branch predictor improves the instruction pipeline process. It executes the instruction based on some conditions.
Explanation:
Number of stages = 18
Branch target conditions are resolved at stage 5. It means up to 8 stages are incorrect branch target.
When branch target is resolved at n^thstage, then number of stalls in that case = n - 1
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11 S12 S13 S14

X
X
X
X
X
X
X
X
S1…….
S2

In this, the branch target is resolved at 9th stage. Number of stalls = 9 - 1 = 8
Notes:
X → represents stall
Question 5
2 / -0.33

A computer uses RAM chips of 1024 × 1 capacity.
How many chips are needed to provide memory capacity of 16K bytes?

A
8

B
16

C
1024

D
128

Solution

RAM chips of capacity 1024 × 1 = 1024 bits
Therefore, for capacity of 16K bytes, i.e. 16 × 1024 × 8 bits,
\({\rm{No\;of\;chips\;needed}} = \frac{{16\; \times \;1024\; \times \;8}}{{1024}} = 128\;chips\)
Question 6
2 / -0.33

Consider a processor in which BR 50 instruction is executed at location 1000. What is the effective address after the execution of the instruction at location 1000? Assume the address is in decimal format.

A
1051-1051

B
10514-10511

C
10517-10516

D
10519-10512

Solution

Concept:
A program counter is a register in a computer processor that contains the address (location) of the instruction in the memory that has to be executed next. As each instruction gets fetched, the Program counter increases its value by 1.
Explanation:
In BR offset is 50
If processor is executing at location 1000
Then program counter will contain 1001
Effective address = Program counter + offset
∴ effective address = 1001 + 50 = 1051
Question 7
2 / -0.33

In a 32-bit processor a fully associative cache is used. The size of cache is 128 KB while that of its block is 16 bytes. If t is the size of tag in bits and i is the size of index field in bits. The value of t × i is _____ (1 word is equal to 1 byte).

A
0-0

B
04-01

C
07-06

D
09-02

Solution

Data
Cache size = 128 KB = 2¹⁷ B
Cache block size = 16 B = 2⁴ B
Physical address = 2³² B = 4 GB //32-bit address
To find:
Number of bits in tag field
Number of bits in Index field
Explanation:
In Fully Associative Mapping:
Physical address:
Tag
Block offset

Physical Address = Tag + block offset
32 = t + 4 // use number of bit
t = 28 bit
In Fully Associative Mapping, index fields is included in tag field there is no separate field for index in fully Associative Mapping. Hence number of bits in index field is zero
∴ t×i = 28 × 0 = 0
Note:
KB is Kilo Byte (2¹⁰ B)

Question 8

2 / -0.33

If instruction X tries to modify some data before it is written by instruction (X-1), it can result in a ________ hazard.

RAR

RAW

WAR

WAW

Solution

Initially A = 20

Instruction	Transaction 1 (T₁)	Transaction 2 (T₂)	Explanation
X – 3	R(A)		T₁: reads A = 20
X – 2	A = A + 50	R(A)	T₁: modify A = 70, T₂: reads A = 20
X – 1	W(A)	A = A + 70	T₁: writes A = 70 T₂: reads A = 90
X		W(A)	T₂: writes A = 90
X + 1

Instruction: X – 1, writes the value 70

Instruction: X, overwrites it with 90

In system, after T₁ and T₂ execution value of A = 90

Ideally value should be 20 + 50 + 70 = 140

These hazards arise due to write after write

Important Points:

RAR → read after read

RAW → read after write

WAR → write after read

WAW → write after write

Question 9
2 / -0.33

A Hypothetical processor can support a maximum of 72 TB memory. If the system is word addressable and the size of word is 4 bytes. What is the least size of the address bus in bits?

A
45-45

B
454-451

C
457-456

D
459-452

Solution

Data:
Memory size = 72 TB
Size of a word = 4 bytes
Calculation:
Memory size = \(\frac{{72}}{4} = 18{\rm{\;Tera\;Word}} = 18 \times {2^{40}}{\rm{\;Word}}\)
Number of bits needed = ⌈log₂ (18 × 2⁴⁰)⌉ = 45 bits
Question 10
2 / -0.33

Which of the following is an efficient method of cache updating?

A
Snoopy writes

B
Write through

C
Write within

D
Buffered write
Solution
Concept:
- In a snooping system, all caches on the bus monitor or snoop the bus to determine if they have a copy of the block of data that is requested on the bus.
- Every cache has a copy of the sharing status of every block of physical memory it has. Multiple copies of a document in a multiprocessing environment typically can be read without any coherence problems.
- For performance reasons, it is important that the snooping function not interfere with the normal operation of a processor and its cache.
Explanation:
Write through protocol
It is also a cache update protocol which updates or invalidates the shared data if needed. This protocol works via broadcasting hence creates a lot of traffic which is not an efficient way.
Write back protocol
It which is also a cache update protocol is based on ownership of a block. This also uses broadcasting similar to write through protocol.
Buffered write
It is an updated form of Write through protocol and uses broadcasting hence it is also no efficient.
Question 11
2 / -0.33

In a computer with average main memory access time is 40 ns if a one-page fault(when a running program accesses a memory page that is mapped into the virtual address space, but not actually loaded into main memory) is generated for every 10⁶ memory accesses, the effective access time for the memory is _____ ns. Let the page fault service time be 20ms. (Give your answer in nearest integer)

A
60-60

B
604-601

C
607-606

D
609-602

Solution

Data:
s = 20 milliseconds
m = 40 nanoseconds
page fault rate = p = \(\frac{1}{10^{6}}\)
m is very large
Formula:
EMAT = p × s + (1 - p) × m
Calculation:
EMAT = (1 ÷ 10⁶ ) × 20 ms + (999999 ÷10⁶) × 40 ns
EMAT = 20 ns + 39.99996 ns
∴ EMAT = 59.99996 ns
If m is considered
Formula:
EMAT = p × (s + m) + (1 - p) × m
EMAT = p × s + m
Calculation:
EMAT = (1 ÷ 106 ) × 20 ms + 40 ns
∴ EMAT = 20 ns + 40 ns = 60 ns
Important Points:
EMAT → effective memory access time
p → page fault rate
s → service time
m → memory access time
Question 12
2 / -0.33

Let a disk pack has 32 surfaces having 1 track per surface, 16 sector per track and 512 bytes per sector. Disk is rotating at 3600 RPM, what is the data transfer in KB if 1 R/W head is available over 32 surfaces?

A
440

B
480

C
500

D
520

Solution

3600 rotations → 1 min
3600 rotations → 60 sec
60 rotations → 1 sec
1 rotation → \(\frac{1}{{60\;}}\;\)sec
1 rotation covers a track
Track capacity = 16 × 512 = 2¹³ bytes
\(\frac{1}{{60\;}}\;\)sec → 2¹³ bytes
∴ data transfer rate = 480 MB/sec
Confusion Points:
Since only 1 R/W. Therefore, data transfer rate = 480 MB/sec
Answer may vary according to the R/W head available
Question 13
2 / -0.33

Consider a 5 GHz (gigahertz) processor with a 4-stage pipeline and stage latencies λ₁, λ₂, λ₃ and λ₄such that \({\lambda _1} = \frac{{4{\lambda _2}}}{5} = \frac{{7{\lambda _3}}}{4} = \frac{{6{\lambda _4}}}{4}\;\). If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is _______GHz, ignoring delays in the pipeline registers. (correct up to two decimal places)

A
6.25-6.25

B
6.254-6.251

C
6.257-6.256

D
6.259-6.252

Solution

Data:
4- stage pipeline with 5 GHz processor
\({\lambda _1} = \frac{{4{\lambda _2}}}{5} = \frac{{7{\lambda _3}}}{4} = \frac{{6{\lambda _4}}}{4} = 84\;x\)
Calculation:
Let λ₁ = 84 x
\(\frac{{4{\lambda _2}}}{5} = 84\) x
∴ λ₂ = 105 x
\(\frac{{7{\lambda _3}}}{4} = 84\;x\)
∴ λ₃ = 48 x
\(\frac{{6{\lambda _4}}}{4} = 84\;x\)
∴ λ₄ = 56 x
As, cycle time = max (all stage delays)
maximum stage delay = 105 x
\({\rm{frequency}} = \frac{1}{{{\rm{cycle\;time}}}}\)
\({\rm{frequency}} = \frac{1}{{105{\rm{\;x}}}}\)
\(5GHz = \;\frac{1}{{105x}}\;\)
\(\frac{1}{x} = 525\;GHz\;\)
Now, longest pipeline, that is, 105 x is split into two equal latency stages: 52.5 x and 52.5 x
Now, maximum stage delay become 84 x
\({\rm{New\;frequency}} = \frac{1}{{84{\rm{x\;}}}} = \frac{{{\rm{\;}}1}}{{84}} \times \frac{1}{{\rm{x}}} = \frac{1}{{84}} \times 525 = 6.25{\rm{\;GHz}}\)
Question 14
2 / -0.33

The size of the physical address space of a processor is 2^a bytes. The word length is 2^b bytes. The capacity of cache memory is C words. The size of the block is 2^d words. For a 2^k-way set-associative cache memory, the length of the tag field in bits is.

A
a – b – c + k + log₂C

B
a – b – d + k + log₂C

C
a + k – log₂C

D
a – b + k – log₂C

Solution

1 word(W) = 2^b bytes
Physical Memory space (PA) = 2^a bytes = 2^{a - b} Words
Cache memory size (CS) = C Words
∴ number of bits in C = \({\log _2}C\)
Block size = 2^d words
Formula to find number of bits in tag in set associative mapping
PA = tag + set + BO
\(a - b = tag + ({\log _2}C - \;d - \;k) + \;d\;\)
\(a - b= tag + {\log _2}C - \;k\;\)
\(tag = a - b + k - {\log _2}C\)
Question 15
2 / -0.33

Consider a 16-bit processor having 32 register. The two types of instruction are A and B respectively. A – type instruction has an opcode followed by two register names and B - type instruction has a opcode, a register name and a 6 – bit immediate value. Type B – instruction format has 19 distinct opcodes. What is the maximum number of distinct A-type opcodes?

A
26-26

B
264-261

C
267-266

D
269-262

Solution

Data:
Instruction length = 16 bits
Number of registers = 32
Bits to represent register = ⌈ log2 (32) ⌉ = 5
Type B - 19 distinct opcodes
Explanation
A-type instruction format =
Opcode
Register
5 bits
Register
5 bits

B-type instruction format:
Opcode
Register
5 bits
Immediate Value
6 bits

Instruction length is given 16, therefore maximum possible encodings = 216
Number of B-type opcodes = 19
A-type Instructions encoding + B-type instructions encoding = Total instructions
Assume the number of A-type opcodes = x
Therefore,
(x × 25 × 25) + (19 × 25 × 26) = 216
÷ b 210 on both side
∴ x + 38 = 26
∴ x = 64 - 38 = 26
Question 16
2 / -0.33

A processor has 72 distinct instruction and 28 general purpose registers. A 16-bit instruction word has an opcode, one register operands and an immediate operand. The maximum decimal value possible of the immediate operand if operand is in 2’s complement is _____.

A
7

B
8

C
16

D
15

Solution

Data
Instruction size = 16
Distinct instruction = 72
General Purpose registers= 28
Formula:
number of bits = ⌈log₂n⌉
Calculation:
Number of bits needed for instruction = ⌈log₂72⌉ = 7
Number of bits needed for register = ⌈log₂28⌉ = 5
Instruction format (32 bit):
Opcode(instruction)
Register
Operand
7 bits
5 bits
x bits

7 + 5 + x = 16
∴ x = 4
Maximum decimal value possible with 4 bits in 2’s complement system = 2^4-1 – 1 = 7
Question 17
2 / -0.33

Consider a processor which generates 32-bit address. A system uses write back policy in 256 KB direct mapped cache. It consists of multiple blocks with each block size as 32 bytes. The cache controller maintains the tag information for each cache block comprising of 1 modified bit, 1 replacement bit and 1 valid bit. The total size of memory needed at the cache controller to store meta-data for the cache is _____ KB?

A
17-17

B
174-171

C
177-176

D
179-172

Solution

Main Memory Size (MM) = 32 bit
Cache Memory Size (CS) = 256 KB = 2¹⁸ B
Block Size (BO) = 32 bytes
Number of cache lines = \(\frac{{{2^{18}}}}{{32}} = {2^{13}}\)
Formula to find number of bits in tag in direct mapping
MM = tag + lines + BO
OR
MM = tag + CS
32 = tag + 18
∴ tag = 14
total size of memory needed at the cache controller to store meta-data for the cache = number of lines × (tag + valid + modified + replacement)
= 2¹³× (14 + 1 + 1 + 1)
= 17 KB
Question 18
2 / -0.33

A 64 Gb DRAM chip is organized as 8 G × 8 memory externally and as 256 K × 256 K square array internally. Refreshing each row takes 20 ns. Each row must be refreshed at least once every 0.05 s. The percentage (rounded to the closet integer) of the time available for performing the memory read/write operations in the main memory unit is ________.

A
89-90

B
894-901

C
897-906

D
899-902

Solution

Data:
Internally: 256 K × 256 K
Refresh row = R = 20 ns
Total refresh period = T = 0.05 s
Number of rows = n = 2⁸ × 2¹⁰ = 2¹⁸
Formula:
Fraction of memory bandwidth lost to refresh cycle \(=\frac{R\times n}{T}\times 100\)
Calculation:
Fraction of memory bandwidth lost to refresh cycle \(=20\times {{10}^{-9}}\times \frac{{{2}^{18}}}{0.05}\times 100\)
Fraction of memory bandwidth lost to refresh cycle = 10.48%
Consider 10% is lost
Therefore, time available for performing the memory read/write operation = (100 – 10)% = 90%
Consider 11% is lost
Therefore, time available for performing the memory read/write operation = (100 – 11)% = 89%
Question 19
2 / -0.33

Consider a system consisting of thirty-two bits virtual address, page size is 16 KB and a 512 lines of translation look-aside buffer organized into 64 sets each. TLB is 8 -way set associative. What is the minimum length of TLB tag in bits (TLB does not store any process ID)?

A
12

B
10

C
14

D
11

Solution

Concept
A translation lookaside buffer (TLB) is a memory cache that is used to reduce the time taken to access a user memory location. It is a part of the chip's memory-management unit (MMU). The TLB stores the recent translations of virtual memory to physical memory and can be called an address-translation cache.
Data
Total virtual address size = VAS = 32 bits.
Page size = PS = 16 KB = 2¹⁴ bytes
Number of entries in TLB = 512
Number of sets = 64 = 2⁶
Tag size
(t bits)
Set offset
(6 bits)
page offset
(14 bits)

Formula:
VAS = tag + set + page offset (in bits)
Number of bits = ⌈ log₂ n ⌉
where is size of memory
Calculation:
32 = t + 6 + 14
∴ t = 12
The minimum length of the TLB tag in bits is 12.
Question 20
2 / -0.33

Consider a system which is byte-addressable. Let a and b be two unsigned numbers of 16 bit each. If ROM stores the result of the multiplication of such numbers, then what is the required size of ROM in GB)?

A
16-16

B
164-161

C
167-166

D
169-162

Solution

Multiplication of two n bit number will result in data = (2n) bits
Multiplication of two n bit number needs 2n address lines
Size of ROM = 2²ⁿ × 2n bits
n = 16
Size of ROM = 2^2×16 × 2(16) bits
Size of ROM = 2³⁷bits
Size of ROM = 2³⁴ bytes
Size of ROM = 16 GB
Important Points:
G → giga, M → mega, K → kilo
1 G = 2³⁰
1 M = 2²⁰
1 K = 2¹⁰
Question 21
2 / -0.33

In a word-addressable processor, a cache block is 32 words. A word size is 4 bytes. The main memory has a latency of 48 nanoseconds with a bandwidth of 8 GB/s. The time requires to fetch the entire cache block is _____.

A
128

B
96

C
52

D
64

Solution

Data:
1 word = 4 bytes
Cache block size = 32 word
Memory latency = 48 ns
Bandwidth = 8 GB/s
Formula:
Total latency = memory latency + block access time
Calculation:
Cache block size = 32 word = 32 × 4 = 128 bytes
8 GB → 1 sec
\(1 B \rightarrow \frac{1}{8 \times 10^{9}s} =\frac{1}{8}\; ns\)
\(128\; B \rightarrow \frac{128}{8 }\;ns \rightarrow 16 \;ns\)
Block access time is 16 ns
Total latency = 48 + 16 = 64
Question 22
2 / -0.33

The size of the data count register of a DMA controller is 24 bits. The processor needs to transfer a file of 4 GB from disk to memory. The memory is word addressable and size of a word is 2 bytes. What is the minimum number of times the DMA controller need to get the control of the system bus from the processor to transfer the file from the hard disk to main memory?

A
128-128

B
1284-1281

C
1287-1286

D
1289-1282

Solution

2 B = 1 W
Transfer file size = 4 GB = 2 GW = 2³¹ W
Data count register = 24 bits
Assume burst mode to minimize DMA controller switching:
In Burst mode, at a time maximum transfer of 2²⁴ W is possible
Minimum number of times the DMA controller needs to get the control
\(= \frac{{{2^{31}}}}{{{2^{24}}}} = {2^7} = 128\)
Question 23
2 / -0.33

In a computer, a memory unit is of size 256 KW where w stands for word. Word size is 32 bits. The instruction has four parts: addressing mode, operation code, register code and address part. An addressing mode part is used to specify one of two-addressing mode (direct or indirect). Register code part is used to specify one of the 64 registers. How many bits are there in addressing mode part, opcode part, register code part, and the address part?

A
1, 6, 7, 18

B
1, 7, 6, 18

C
1, 7, 5, 19

D
1, 5, 6, 20

Solution

Data:
Memory unit = 256 KW = 2¹⁸ W
1 word = 32 bits = 4 B
Binary instruction code stored in 1 word of memory
Instruction divided as follows,
addressing mode operation mode register code address
1 bit x bits 6 bits 18 bits
Calculation:
Addressing mode = 1 bit for direct or indirect
Register code = ln (64) = 6 bits
Since registers are already addressed, only memory needs to be addressed
Address part = ln (2¹⁸) = 18 bits
Operation mode = 32 – 1 – 6 – 18 = 7 bits
Therefore, bits for addressing mode part, opcode part, register code part and the address part = (1, 7, 6, 18)

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addressing mode	operation mode	register code	address
1 bit	x bits	6 bits	18 bits

Opcode(instruction)	Register	Operand
7 bits	5 bits	x bits

Computer Organization and Architecture Test 1

Result

Computer Organization and Architecture Test 1

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SHARING IS CARING

Question 1

(k mod y)

(k mod xy)

(k mod x)

(k mod 2xy)

Solution

Question 2

2.45-2.46

2.454-2.461

2.457-2.466

2.459-2.462

Solution

Question 3

T1 + (1 – H) × T2

(1 – H) × T1 + T2

(T1 + T2) (1 – H)

T­1­ + T2 (1 + H)

Solution

Question 4

8-8

84-81

87-86

89-82

Solution

Question 5

8

16

1024

128

Solution

Question 6

1051-1051

10514-10511

10517-10516

10519-10512

Solution

Question 7

0-0

04-01

07-06

09-02

Solution

Question 8

RAR

RAW

WAR

WAW

Solution

Question 9

45-45

454-451

457-456

459-452

Solution

Question 10

Snoopy writes

Write through

Write within

Buffered write

Solution

Question 11

60-60

604-601

607-606

609-602

Solution

Question 12

440

480

500

520

Solution

T₁ + (1 – H) × T₂

(1 – H) × T₁ + T₂

(T₁ + T₂) (1 – H)

T1 + T₂ (1 + H)

a – b – c + k + log₂C

a – b – d + k + log₂C

a + k – log₂C

a – b + k – log₂C