Computer Organization and Architecture Test 2

Write back Cache policy:

In this data is written to cache, and the i/o is performed. In this update are made to the cache. When an update occurs, a dirty bit associated with the line is set. Then, when a block is replaced it is written back to main memory if and only if the dirty bit is set.

Advantages:

• It minimizes memory writes.
• Having low latency and high throughput

Disadvantages:

• Portions of main memory are invalid and hence accesses by I/O modules can be allowed only through the cache. This makes the complex circuitry. 

Concepts:

• Conflict misses: Even when empty place is available, block is trying to occupy already filled line leads to conflict miss.
• In direct mapped, memory reference(x) should be place in x mod C where C is number blocks in cache. In set associative mapped, memory reference(x) should be place in x mod S where S is number sets in cache. Hence conflict miss occurs in the case of set associative or direct mapped block placement strategies.

• In a fully associative mapping, block number of Main Memory is equal to tag size, therefore no such constraint to put memory reference in a specify set or lines of a cache and hence no Conflict miss

Data:

radius = 21 cm

density = 8 KB/cm

Formula:

Circumference of track = 2 π r

Calculation:

Circumference of track = 2×22/7× 21= 132 cm

1 cm → 8 KB

∴ 132 cm → 1056 KB

the capacity of the track is 1056 KB

Data:

1 word → 2 byte

Main memory (MM) = 2 MB = 2²¹ bytes = 2²⁰ word

Block size (B0) = 16 Bytes = 8 words = 2³ word

Number of lines (lines) = 1024 = 2¹⁰

Formula:

MM = tag + lines + B0 (in bits)

20 = tag + 10 + 3

∴ tag = 7 bits.

Address: (AF9CB)_H

Tag = (1010111)₂

Line = (1100111001)₂

Data:

Word size = 64 bits = 8 Bytes

Cache block size= 256 Bytes

Hit rate = 0.94

Cache access time = T_c = 3ns

Formula:

The average memory access time in cache with hit rate ‘h’ is given by

AMAT= h × T_c + (1 – h) × (T_c + T_m)

where T_m is main memory access time. T_m comprises of time taken to move the words of a block from main memory.

Calculation:

Number of words in one cache block= 256 ÷ 8 = 32 words.

Now, 1^st word would take 20 ns to bring from main memory into cache memory and remaining 31 words would take 5ns.

AMAT= 0.94 × 3 + (1 – 0.94) × (3 + 20 + 31* 5)

           = 2.82 + 10.68 = 13.5ns

Important Point:

Parallel access:

AMAT= h × T_c + (1 – h) × T_m

AMAT= 13.3

NOTE:

Fully associative mapped:

1 Word = 2 bytes

Tag size = 24 bits

Block size = 64 bytes = 32 word = 25 word

Physical address = PA bits

Physical address (PA) = tag + block offset …………. (bits)

PA = 24 + 5 = 29

Set associative mapped:

Physical address size = 229 word = 512 MegaWord

number of Blocks = 1 M = 220

\(number\;of\;sets = \frac{{blocks}}{{blocks\;per\;set}} = \frac{{{2^{20}}}}{4} = {2^{18}}\)

PA = tag + set + block offset

29 = tag + 18 + 5

Data:

Refresh row = R = 40 ns

Total refresh period = T = 5 s

Number of rows = n = 2²⁵

Formula:

Fraction of memory bandwidth lost to refresh cycle \(=\frac{R\times n}{T}\)

Calculation:

Fraction of memory bandwidth lost to refresh cycle \(=40\times {{10}^{-9}}\times \frac{{{2}^{25}}}{5}\ = 0.2684\)

Data:

Seek time = 32ns,

rotational rate = 360 rpm,

1 Track size =512 sectors × 512 Byte/sectors=256KB

Formula:

Time Taken to read four continuous sectors = Seek time + Rotational delay + Transfer time

Data transfer rate = Number of bytes transferred in one second

Calculation:

Seek Time = 32 * 10^-9 = 0.000000032 secs ≈ 0.0000 sec

Rotational latency = 360 rotation takes 60 sec

\(\therefore 1{\rm{\;rotation\;}} = {\rm{\;}}\frac{1}{6}\;sec\)  

Rotational latency = Half the rotation time.

\({\rm{Rotational\;latency\;}} = \;\frac{1}{{12}} = 0.0833\;sec\) 

Transfer Time  

1 track can read in one rotation and 1 track can read 256KB but here we have to read 4 sectors

4 sectors size will be = 4 × 512 B = 2KB

\(256{\rm{\;KB\;takes}} \to \frac{1}{6}{\rm{sec\;\;}}\)

\(1{\rm{\;KB\;takes}} \to \frac{1}{{256 \times 6}}{\rm{\;sec}}\)

\(2{\rm{\;KB\;takes}} \to {\rm{\;}}\frac{2}{{256 \times 6}} = 0.00130\) 

Total Time = 0.0000 + 0.0833 + 0.0013 = 0.0846 secs

Data Transfer Rate = Number of bytes transferred in one unit time ( 1 sec )

\(256{\rm{\;KB\;takes}} \to \frac{1}{6}{\rm{sec}}\)

∴ In 1 sec = 6 × 256 KB = 1536 KB

∴ date transfer rate = 1536 KBps

Hence option 2 is the correct answer.

Data:

Cache C1,

T₁ = 3 cycle

Miss ratio = 1 – p = 0.1

Hit ratio = p

Cache C2

T₂ = 15 cycle

Miss ratio = 1 – q = 0.2

Hit ratio = q

Main memory:

Hit ratio = 100% = 1

T₃ = 50 cycle

Formula:

T_avg = T₁ + (1 – p)T₂ + (1 – p)(1 – q)T₃

Calculation:

T_avg = 3 + (0.1) × 15 + ((0.1) × (0.2) × 50 = 5.5 cycle

Important Points:

In two level in serial manner,

Tavg = H1T1 + (1- H1)(T1 + T2)

Tavg = T1 + (1- H1)(T2)

Similarly three level in serial manner

Tavg = H1T1 + (1 - H1)H2(T1 + T2) +(1- H1)(1 - H2)(T1 + T2 + T3)

Tavg = T1 + (1- H1)T2 + (1 - H1)(1 -H2)T3

Use any formula for given serial level