Computer Organi...

The disadvantage of write back strategy in cache is that:

Which of the following is/are true about conflict miss?

Consider a disk with the radius of the innermost track is 21 cm with 8 KB/cm. What is the capacity of the track in KB?

Consider a word addressable system. The main memory is of size 2 MB and direct-mapped cache containing 1024 lines. The size of block is 16 bytes while each word consists of 2 bytes. What is the tag for memory address (AF9CB)_H?

A direct-mapped cache memory of 1 MB has a block size of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is _______.

Consider a computer system that is word addressable and each word size is 2 bytes. A cache which is fully associative with tag size equal to 24 bits and block size is 64 bytes. Now, same cache is changed to 4 way set associative mapping, find the size of tag in set associative organization which contains 1 M blocks?

Consider a hypothetical system, a 48 – bit width main memory with a capacity 256 TB is build using 64 T × 8-bit DRAM chips. The number of rows of memory cells in the DRAM is 2²⁵. The time taken to perform one Refresh operation is 40 ns. The refresh period is 5 s. Fraction of total memory bandwidth is lost to refresh cycle is _____ (up to two decimal places).

Consider the disk which has average seek time of 32 ns and rotational rate of 360 rpm(round per minute), Each track of the disk has 512 sectors, each of size 512 bytes.

Consider the cache memory and the main memory connected serially. If the word in not found in cache memory, then it is found in the main memory. Let C1 and C2 be the cache memory in a two-level cache system. The access time of C1 is 3 cycle, access time of C2 is 15 cycle and the access time of main memory is 50 cycle. The miss rate of is 10% and 20% of C1 and C2 respectively. The average memory access time of the system is _____ cycle.