Computer Organization and Architecture Test 3

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Computer Organization and Architecture Test 3

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Weekly Quiz Competition

Question 1
1 / -0

One instruction tries to write an operand before it is written by previous instruction. This may lead to a dependency called

A
True dependency

B
Anti-dependency

C
Output Dependency

D
Control hazard

Solution

Option 1: True dependency
True dependency is when Read-after-Write or RAW occurs
Option 2: Anti-dependency
Anti-dependency is when Write-after-Read or WAR occurs
Option 3: Output Dependency
Output dependency is when Write-after-Write or WAW occurs
Option 4: Control hazard
Control Hazard is when pipeline makes wrong decisions on branch prediction
Question 2
1 / -0

We have 10-stage pipeline, where the branch target conditions are resolved at stage 5. How may stalls are there for an incorrectly predicted branch?

A
5

B
6

C
7

D
4

Solution

Concept:
Branch condition guesses the outcome of conditional operations and then find the next result. Branch predictor improves the instruction pipeline process. It executes the instruction based on some conditions.
Explanation:
Number of stages = 10
Branch target conditions are resolved at stage 5. It means upto 4 stages are incorrect branch target.
When branch target is resolved at nth stage, then number of stalls in that case = n -1
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10

X
X
X
X
S1
S2
S3
S4
S5……….

In this, branch target is resolved at 5^th stage. Number of stalls = 5-1 = 4
Notes:
X → represent stalls
Question 3
1 / -0

Consider a four-stage pipeline with stage latencies 3 ns, 4 ns, 7ns, and 5 ns respectively. If registers are placed between the stages with a latency of 1 ns. What is the clock frequency of the given processor in MHz?

A
100

B
115

C
125

D
130

Solution

Time taken by ideal condition pipeline for 1 instruction (Tp) = max(3, 4, 7, 5) + 1 = 8 ns
Frequency = \(\frac{1}{T_p} = \frac{1}{8} = 0.125 \times 10^9 Hz= 125 \;MHz \)
Question 4
1 / -0

In a 4- stage pipeline processor. The number of cycles needed by the five instructions N₁, N₂, N₃, N₄ and N₅

IF
ID
EX
WB
N₁
1
1
2
1
N₂
2
1
3
1
N₃
1
2
1
1
N₄
3
2
1
2
N₅
1
2
2
1

What is the number of cycles needed to execute the following loop?
for(int j = 0; j < 1; j++)
{
N₁;
N₂;
N₃;
N₄;
N₅;
}

A
12

B
13

C
14

D
15

Solution

j = 0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
N1
IF
ID
EX
EX
WB

N2

IF
IF
ID
EX
EX
EX
WB

N3

IF
ID
ID

EX
WB

N4

IF
IF
IF
ID
ID
EX
WB
WB

N₅

IF

ID
ID
EX
EX
WB

Therefore the number of cycles required to execute 5 instruction is 14.
Question 5
1 / -0

A pipelined processor executing with a constant clock rate has 5 stages. The five stages are Fetch, Decode, Execute, Memory Access and Write Back. Latency of the stages are 100, 80, 120, 150 and 140 nanoseconds respectively. If a register which has a delay of 10 ns is used between the different stages of the pipelined processor. The time taken to execute 2001 instruction for a pipelined processor is _____ microseconds.

A
320-321

B
3204-3211

C
3207-3216

D
3209-3212

Solution

In pipeline, time taken 1 instruction = Max(100, 80, 120, 150 and 140) + 10 = 160 ns
1st instruction time taken = 1 × 5 × 160 ns
Remaining 2000 instruction = 2000 × 1600 ns
Total time taken = (1 × 5 × 160 + 2000 × 160) ns
Total time taken = 2005 × 160 = 320800 ns
320800 = 320.8 μs ≈ 321 μs
Question 6
1 / -0

Consider the following processor (ns stands for nanoseconds). Assume that the pipeline registers have zero latency.
P1: Four-stage pipeline with stage latencies 2 ns, 3 ns, 3 ns, 2 ns.
P2: Four-stage pipeline with stage latencies 2 ns, 2.5 ns, 2.5 ns, 2.5 ns.
P3: Five-stage pipeline with stage latencies 1 ns, 2 ns, 3 ns, 1.2 ns, 2 ns
P4: Five-stage pipeline with stage latencies 1.5 ns, 1.5 ns, 2 ns, 1 ns, 2 ns
Which processor has the lowest peak clock frequency?

A
P4

B
P3

C
P2

D
P1

Solution

Time taken by P1 = max( 2 ns, 3 ns, 3 ns, 2 ns) = 3 ns
∴ Frequency of P1 = \(\frac{1}{{3\;ns}} = 0.33\;GHz\)
Time taken by P2 = max(2 ns, 2.5 ns, 2.5 ns, 2.5 ns) = 2.5 ns
∴ Frequency of P2 = \(\frac{1}{{2.5\;ns}} = 0.4\;GHz\)
Time taken by P3 = max(1 ns, 2 ns, 3 ns, 1.2 ns, 2 ns) = 3 ns
∴ Frequency of P3 = \(\frac{1}{{3\;ns}} = 0.33\;GHz\)
Time taken by P4 = max(1.5 ns, 1.5 ns, 2 ns, 1 ns, 2) = 2 ns
∴ Frequency of P4 = \(\frac{1}{{2\;ns}} = 0.5\;GHz\)
∴ Clock Frequency of P1 and P3 is lowest.
Question 7
1 / -0

Consider a 5-stage pipeline are 3, 5, 8, 2 and 4 nanoseconds in which 1^st stage is with 3 nanosecond, 2^nd stage is with 5 nano seconds and so on. The third stage is replaced with a functionally equivalent design involving two stages with 5 and 4 nanoseconds respectively. The throughput increase of the pipeline is _______ percent.

A
60-60

B
604-601

C
607-606

D
609-602

Solution

In 5-stage pipeline,
Time for 1 instruction = t = max(3, 5, 8, 2, 4) ns = 8 ns
In 1 second number of instructions = \(\frac{1\times 10^9}{8} = 0.125 \times 10^9\)
In 6-stage pipeline,
Time for 1 instruction = t = max(3, 5, 5, 4 , 2, 4) ns = 5 ns
In 1 second number of instructions = \(\frac{1\times 10^9}{5} = 0.2 \times 10^9\)
Efficiency = \((\frac{0.2 \times 10^9 - 0.125 \times 10^9}{0.125 \times 10^9})\times 100 =(\frac{0.075}{0.125})\times 100\)
Efficiency = 60%
Question 8
1 / -0

In a non-pipelined processor, to execute one instruction 5 cycles are needed. The clock speed of non-pipelined processor is 4 GHz. If same processor is changed to pipelined processor having 6 stages. The clock rate of pipelined processor is changed to 3 GHz. What is the speedup achieved in this pipelined processor?(Assume no stalls in pipelined processor)

A
3.7-3.8

B
3.74-3.81

C
3.77-3.86

D
3.79-3.82

Solution

Data:
Clock rate for non-pipeline = 4 GHz
CPI for non-pipeline = 5
Clock rate for pipeline = 3.5 GHz
CPI for pipeline = 1
Formula:
Speed up = \(\frac{{Execution\;time\left( {non\;pipeline} \right)}}{{Execution\;time\;\left( {pipeline} \right)}}\)
Execution time = CPI × Cycle time (CPI is cycles per instruction)
\({\rm{Cycle\;time\;}} = \frac{1}{{{\rm{clock\;rate}}}}\)
Calculation:
Execution time for non-pipeline = \(5 \times \frac{1}{{4}} = 1.25\;ns\)
Execution time for pipeline = \(1 \times \frac{1}{3} = 0.33\;ns\)
Speed up = \(\frac{{1.25}}{{\frac{1}{3}}} = 3.75\)
Question 9
1 / -0

Consider a pipeline CPU with a single arithmetic logic unit (ALU)
Which one of the statements may cause a hazard?

A
ith instruction and i + 1st instruction requires ALU at the same time

B
The i + 1st instruction uses the result of ith instruction as an operand

C
When more than one instruction tries to access the same resource in the same cycle

D
Conditional jump instruction

Solution

Option 1:
Structural hazards arise from resource conflicts when the hardware cannot support all possible combinations of instructions in simultaneous overlapped execution.
Option 2:
Data hazards arise when an instruction depends on the result of previous instruction in a way that is exposed by the overlapping of instructions in the pipeline.
Option 3:
A resource conflict ( Structural dependency )is a situation when more than one instruction tries to access the same resource in the same cycle. A resource can be a register, memory, or ALU.
Option 4:
Control hazards arise from the pipelining of branches and other instructions that change the program counter.
Question 10
1 / -0

Consider a 5-stage pipeline with stage delays 8 ns, 2 ns, 12 ns, 15 ns, 9 ns. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2.5 ns. The speedup factor achieved by pipeline implementation over non – pipeline implementation is 1.05. Average execution time for non-pipeline implementation is 1911 ns. Find the number of instructions.

A
100-100

B
1004-1001

C
1007-1006

D
1009-1002

Solution

Speed up factor achieved by pipeline implementation over non – pipeline implementation = \(\frac{{Average\;execution\;tim{e_{non - pipeline}}}}{{Average\;execution\;tim{e_{pipeline}}}}\)
1.05 = \(\frac{{1911}}{{Average\;execution\;tim{e_{pipeline}}}}\)
Average execution time_pipeline = 1820
No. of stages (k) = 5
Cycle time = T_P = max(stage delay + buffer delay)
T_p = 15 + 2.5 = 17.5 ns
Average execution time_pipeline = (k + n - 1) T_p
1820 = (5 + n – 1) 17.5
1820 = (4 + n)17.5
1820 = 70 + 17.5n
1750 = 17.5n
n = 100

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S1	S2	S3	S4	S5	S6	S7	S8	S9	S10
	X	X	X	X	S1	S2	S3	S4	S5……….

	IF	ID	EX	WB
N₁	1	1	2	1
N₂	2	1	3	1
N₃	1	2	1	1
N₄	3	2	1	2
N₅	1	2	2	1

Computer Organization and Architecture Test 3

Result

Computer Organization and Architecture Test 3

Score

-

Rank

-

SHARING IS CARING

Question 1

True dependency

Anti-dependency

Output Dependency

Control hazard

Solution

Question 2

5

6

7

4

Solution

Question 3

100

115

125

130

Solution

Question 4

12

13

14

15

Solution

Question 5

320-321

3204-3211

3207-3216

3209-3212

Solution

Question 6

P4

P3

P2

P1

Solution

Question 7

60-60

604-601

607-606

609-602

Solution

Question 8

3.7-3.8

3.74-3.81

3.77-3.86

3.79-3.82

Solution

Question 9

ith instruction and i + 1st instruction requires ALU at the same time

The i + 1st instruction uses the result of ith instruction as an operand

When more than one instruction tries to access the same resource in the same cycle

Conditional jump instruction

Solution

Question 10

100-100

1004-1001

1007-1006

1009-1002

Solution

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