Computer Organization and Architecture Test 4

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Computer Organization and Architecture Test 4

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Question 1

1 / -0

A micro programmed control unit

Is faster than a hardwired unit

Facilitates easy implementation of a new instruction

Is useful when small programs are to be run

All of the above

Solution

Difference between Microprogrammed Control Unit and Hardwired Control Unit

Microprogrammed Control Unit	Hardwired Control Unit
It is implemented by programming	It is a circuitry approach
CISC style instructions	RISC style instructions
Modifications are easy as it will require the change in the code section only.	Modification is difficult as the control unit is hardwired
It works well for complex instructions also	It works well for simple instructions
Implementing microprograms is not costly	Implementing hardwired structure is costly
Slower execution	Faster execution

Therefore, a micro programmed control unit facilitates easy implementation of a new instruction

Question 2
1 / -0

Consider the processor of a supercomputer which can support a maximum memory of 32 TB. Assume that memory is word addressable and a word consists of 8 bytes. The size of the address bus of the processor is at least _____ bits.

A
42-42

B
424-421

C
427-426

D
429-422

Solution

1 Terabyte = 2⁴⁰
Main Memory Size = 32 TB
= 32 × 2⁴⁰ B
= 4× 2⁴⁰ W
= 2⁴² W
∴ size of the address bus of the processor is at least 42 bits.
Question 3
1 / -0

Consider a memory unit of size 200 K × 32, where first component represents the number of words and that the second component represents the number of bits per word. What will be the number of address lines and input-output data lines?

A
18 address lines

B
22 address lines

C
32 data lines

D
24 data lines

Solution

Concept:
Address line:
An address line is basically referred to the physical connection between a CPU/Chipset and memory. They specify which addresses to access in memory. When there are k address lines, then 2k memory word can be accessed.
Data line:
Data lines provide the information to be stored in memory. It represents the number of bits in the word.
Calculation:
Here, it is given that memory unit size = 200 K × 32
where 96 K represents the number of words.
16 represents the number of bits per word.
As, 128 < 200 ≤ 256 so, we have to take 128 i.e. 28.
Number of words = 200 K = 28 × 210 = 2 18
It means address line to access those words are 18
Number of input-output data lines = number of bits in a word = 32
Question 4
1 / -0

Cycle stealing mode of DMA operation involves

A
DMA-controlled taking on the address, data and control buses, while a block of data is transformed between memory and the I/O device

B
While the microprocessor is executing a programme, an interface circuit takes control of the address, data and control buses, when not in use by the microprocessor

C
The data transfer takes place, between I/O device and memory during every alternate clock cycle

D
The DMA controller working for the microprocessor to finish execution of the programme and then takes over the buses
Solution
There are three modes of DMA operation:
1. Burst mode DMA,
- the CPU can be put on hold while the DMA transfer occurs and a full block of possibly hundreds or thousands of bytes can be moved
- For the entire duration of the transfer, the CPU stays idle and the DMA controller and the peripheral device gets complete access to the system buses
2. Transparent mode
- It takes the most time to transfer a block of data, yet it is also the most efficient mode in terms of overall system performance
- In transparent mode, the DMA controller transfers data only when the CPU is performing operations that do not use the system buses
3. Cycle stealing mode
- In this only one byte of data transferred in a single request, after one byte of data transfer, the control of the system bus is given back to the CPU transferring one byte of data per request, until the entire block of data has been transferred.
Question 5
1 / -0

In a micro program control unit, a micro-instruction needs at most 2-control signal to active. Also the control unit required to generate 50 control signal in total. The minimum number of bits required in the control word to generate the required control signal is ____.

A
11-11

B
114-111

C
117-116

D
119-112

Solution

Concept:
vertical microprogramming, minimum bits will be needed
Data:
Control signal = 50
Maximum number of control signal active = 2
Calculation:
One signal + 1 signal + 2 signals
1 + 50C1 + 50C2 = 1 + 50 + (25 × 49) = 1276
the minimum number of bits required in the control word to generate the required control signal = ⌈ log2 1276⌉ = 11
Question 6
1 / -0

How many bytes of data can be sent in 33 seconds over a serial link with baud rate of 6000 in asynchronous mode with odd parity and two stop bits in the frame?

A
18000

B
15000

C
16500

D
None of these

Solution

Baud rate = 6000 bits/sec
Number of bits needed to send 1 byte of data
= 1(start bit) + 8(data) + 1 (parity) + 2 (stop) = 12 bits
\(\therefore transfer\;rate = baud\;rate \times \frac{8}{{12}} = 6000 \times \;\frac{8}{{12}} = 4 \times {10^3}\;bits/sec\)
1 second → 500 byte
∴ 33 seconds → 16500 bytes
Question 7
1 / -0

Consider a hypothetical system that uses Direct Memory mode access(DMA) mode to transfer the data from the hard disk to the main memory. If the size of the DMA controller’s data count register is 32 bits. A file of 1024 GB needs to transfer from disk to memory. What is the minimum number of times the DMA controller needs to get the control of the system bus if the system is byte-addressable?

A
256-256

B
2564-2561

C
2567-2566

D
2569-2562

Solution

Concepts:
During burst transfer, data equal to count of the register could be sent at a time.
Data:
Data count register = 232 bits
File size = 1024 GB = 2¹⁰ × 2³⁰ = 2⁴⁰ Byte
Formula
Minimum number of times the DMA controller needs to get the control = \(\lceil\frac{{File\;size}}{{Data\;count\;register}}\rceil\)
Calculation:
Minimum number of times the DMA controller needs to get the control = \(\lceil\frac{{2^{40}\;B}}{{{2^{32 }B}}}\rceil\) = 2⁸ = 256
Question 8
1 / -0

Consider the following processor design characteristics.
I. Register-to-register arithmetic operations only
II. Fixed-length instruction format
III. Hardwired control unit
Which of the characteristics above are used in the design of a RISC processor?

A
I and II only

B
II and III only

C
I and III only

D
I, II and III

Solution

Instructions length cannot vary in RISC usually it's 32 bit.
For CISC it can be between 16 to 64 bits.
The hardwired control unit is used when number and size of instructions is fixed to increase processing speed.
Register to register operations is always possible in RISC.
CISC can have memory to memory and memory to register instructions also.
Question 9
1 / -0

Which of the below statements is/are FALSE?

A
In polling, the CPU periodically checks the status bits to know if any device needs its attention.

B
When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt

C
During DMA, both the CPU and DMA controller can be bus masters at the same time.

D
Daisy chaining is used to assign priorities in attending interrupts.

Solution

Statement I: TRUE.
In the polling method, the CPU polls each device to check status bits to find out if the device has raised any interrupt. It is a software method.
Statement II: FALSE
In the vectored interrupt, a vector address is given to the CPU to identify the source of the interrupt. For example, in 8085 µP, RST 4.5 is a vectored interrupt. Here, 4.5 is the interrupt vector which gives the vector address as 4.5 × 8 = (36)10 = (0024)16
Statement III: FALSE
In DMA mode, either the CPU or the DMA controller would gain control of the system bus time, but not both. Accordingly, the CPU would be either in a busy state or Hold state. It would be in a busy state until I/O device prepares the data and would go to Hold state when I/O device starts transferring data to the main memory via the DMA controller.
Statement IV: TRUE
In daisy-chaining method of interrupt handling, the devices are connected serially in such a manner that nearest device to the CPU has the highest priority, followed by the next device and so on.
Question 10
1 / -0

No of bits required in control word for horizontal and vertical micro-programming with following signal specifications would be:
s1: 10 signals
s2: 12 signals
s3: 30 signals

A
40, 8

B
52, 13

C
42, 8

D
None of these
Solution
- In the Horizontal micro-programmed control unit, the control signals are represented in the decoded binary format. Here ‘n’ control signals require n bit encoding.
number of bits in control word of Horizontal micro-programmed control unit
= 10 + 12 + 30 = 52
- In the Vertical micro-programmed control unit, the control signals are represented in the encoded binary format. Here ‘n’ control signals require ⌈log2n⌉ bit encoding.
number of bits in control word of Horizontal micro-programmed control unit
= ⌈log210⌉ + ⌈log212⌉ + ⌈log230⌉ = 4 + 4 + 5 = 13 bits

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Computer Organization and Architecture Test 4

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Question 1

Is faster than a hardwired unit

Facilitates easy implementation of a new instruction

Is useful when small programs are to be run

All of the above

Solution

Question 2

42-42

424-421

427-426

429-422

Solution

Question 3

18 address lines

22 address lines

32 data lines

24 data lines

Solution

Question 4

DMA-controlled taking on the address, data and control buses, while a block of data is transformed between memory and the I/O device

While the microprocessor is executing a programme, an interface circuit takes control of the address, data and control buses, when not in use by the microprocessor

The data transfer takes place, between I/O device and memory during every alternate clock cycle

The DMA controller working for the microprocessor to finish execution of the programme and then takes over the buses

Solution

Question 5

11-11

114-111

117-116

119-112

Solution

Question 6

18000

15000

16500

None of these

Solution

Question 7

256-256

2564-2561

2567-2566

2569-2562

Solution

Question 8

I and II only

II and III only

I and III only

I, II and III

Solution

Question 9

In polling, the CPU periodically checks the status bits to know if any device needs its attention.

When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt

During DMA, both the CPU and DMA controller can be bus masters at the same time.

Daisy chaining is used to assign priorities in attending interrupts.

Solution

Question 10

40, 8

52, 13

42, 8

None of these

Solution

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