Computer Organi...

A micro programmed control unit

Consider the processor of a supercomputer which can support a maximum memory of 32 TB. Assume that memory is word addressable and a word consists of 8 bytes. The size of the address bus of the processor is at least _____ bits.

Consider a memory unit of size 200 K × 32, where first component represents the number of words and that the second component represents the number of bits per word. What will be the number of address lines and input-output data lines?

Cycle stealing mode of DMA operation involves

In a micro program control unit, a micro-instruction needs at most 2-control signal to active. Also the control unit required to generate 50 control signal in total. The minimum number of bits required in the control word to generate the required control signal is ____.

How many bytes of data can be sent in 33 seconds over a serial link with baud rate of 6000 in asynchronous mode with odd parity and two stop bits in the frame?

Consider a hypothetical system that uses Direct Memory mode access(DMA) mode to transfer the data from the hard disk to the main memory. If the size of the DMA controller’s data count register is 32 bits. A file of 1024 GB needs to transfer from disk to memory. What is the minimum number of times the DMA controller needs to get the control of the system bus if the system is byte-addressable?

Consider the following processor design characteristics.

I. Register-to-register arithmetic operations only

II. Fixed-length instruction format

III. Hardwired control unit

Which of the characteristics above are used in the design of a RISC processor?

Which of the below statements is/are FALSE?

No of bits required in control word for horizontal and vertical micro-programming with following signal specifications would be:

s1: 10 signals

s2: 12 signals

s3: 30 signals