Digital Electronics Test 2

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Digital Electronics Test 2

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Weekly Quiz Competition

Question 1
2 / -0.33

An 8 –bit D/A converter has step size of 20 mV. The full-scale output and the resolution will be nearly

A
5.1 V and 0.3%

B
4.6 V and 0.4%

C
5.1 V and 0.4%

D
4.6 V and 0.3%

Solution

Concept:
Resolution is defined as the smallest change in the analog output voltage corresponding to a change of one bit in the digital output.
The percentage resolution of an n-bit DAC is given by:
\(\%R = \frac{1}{{{2^n} - 1}} × 100\)
Also, the full-scale output for the given step size (Δ) is given by:
V_FS = (2ⁿ - 1) × Δ
where 2ⁿ - 1 = Number of levels
Calculation:
Given Δ = 20 mV and n= 8.
The full-scale output will be:
VFS = (28 - 1) × 20 mV
V_FS = 5.1 V
also, the percentage resolution will be:
\(\%R = \frac{1}{{{2^8} - 1}} × 100\)
%R = 0.4 %

Question 2

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Match the Boolean expression with its minimal realization

	Boolean expression		Minimal realization
P	X̅ Y̅ Z̅ + X̅ Y Z̅ + X̅ Y Z	K	X (Y + Z)
Q	X Y Z + X Y̅ Z + X Y Z̅	L	X̅ (Y + Z̅)
R	X Y + X Y Z + X Y Z̅ + X̅ Y Z	M	Z
S	X̅ Y̅ Z + X̅ Y Z + X Y̅ Z + X Y Z	N	Y (X + Z)

P – K, Q – L, R – N, S - M

P – L, Q – K, R – N, S - M

P – L, Q – N, R – M, S - K

P – M, Q – K, R – L, S - N

Solution

(P) X̅ Y̅ Z̅ + X̅ Y Z̅ + X̅ Y Z

= X̅ Y̅ Z̅ + X̅ Y̅ Z̅ + X̅ Y Z̅ + X̅ Y Z

= X̅ Z̅ (Y̅ + Y) + X̅ Y (Z̅ + Z)

= X̅ Z̅ + X̅ Y

= X̅ (Y + Z̅) = L

(Q) X Y Z + X Y̅ Z + X Y Z̅

= X Y Z + X Y̅ Z + X Y Z + X Y Z̅

= X Z (Y + Y̅) + X Y (Z + Z̅)

= XZ + X Y

= X (Y + Z) = K

(R) X Y + X Y Z + X Y Z̅ + X̅ Y Z

= XY (1 + Z + Z̅) + X̅ Y Z

= X Y + X̅ Y Z

= Y (X + X̅ Z) = Y (X + Z) = N

(S) X̅ Y̅ Z + X̅ Y Z + X Y̅ Z + X Y Z

= X̅ Z (Y̅ + Y) + XZ (Y̅ + Y)

= X̅ Z + X Z = Z (X̅ + X)

= Z = M

Question 3
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In the truth table of an N-input OR gate, in the column for the output of the gate,

A
the number of zeros is equal to N.

B
the number of zeros is always 1.

C
the output is zero if any one of the input is zero

D
the number of times a zero occurs is a complex function of N.

Solution

A two input OR gate truth table is shown below:

From the truth table of OR gate it is clear tha output is 0’s only when all the inputs are 0’s otherwise for all other input combination outpu is always 1's. Hence, in the column for the outpu of the OR gate, the number of zeros is always 1's.
Question 4
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A
X when n is even

B
Zero when n is odd

C
X when n is odd

D
Zero when n is even

Solution
Question 5
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The simplified version of the logic circuit shown below consists of

A
a NAND gate

B
a AND gate and a NOT gate

C
an X-OR gate

D
an OR gate

Solution
Question 6
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The circuit shown in figure is a ECL OR-AND- INVERTER circuit. The output Z is

A
0

B
X + Y

C
1

D

Solution

In case of ECL circuit, the floating inputs are considered as logic ‘0’. Hence output
Question 7
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A switching function of four variable, f (w, x y, z) is to equal the product of two other function f₁ and f₂, of the same variable f = f₁f₂. The function f and f₁ are as follows :

f = ∑m(4,7,15)

f = ∑m(0,1,2, 3, 4,7, 8,9,10,11,15)

The number of full specified function, that will satisfy the given condition, is

A
32

B
16

C
4

D
1

Solution

f = ∑m(4,7,15)

f₁ = ∑m(0,1,2, 3, 4,7, 8,9,10,11,15)

f₂ = ∑m(4,7,15) + ∑dc(5, 6, 12, 13, 14)

There are 5 don't care condition. So 2⁵ = 32 different functions f₂
Question 8
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A four-variable switching function has minterms m₆ and m₉. If the literals in these minterms are complemented, the corresponding minterm numbers are

A
m₃ and m₀

B
m₉ and m₆

C
m₂ and m₀

D
m₆ and m₉

Solution
Question 9
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The minimum function that can detect a “divisible by 3’’ 8421 BCD code digit (representation D₈ D₄ D₂ D₁) is given by

A

B

C

D

Solution
Question 10
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A
π(1, 2, 4, 5, 7)

B
∑(1, 2, 4, 5, 7)

C
∑(0, 3, 6)

D
None of Above

Solution
Question 11
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If f(t) is 1 MHz sinusoid with 1 V_p-p and sampling frequency f_s is 25 kHz, the output:

A
0V

B
DC value anywhere between -1 V and +1 V

C
DC value anywhere between -0.5 V and +0.5 V

D
1 V_p-p 1 MHz sinusoid
Solution
Concept:

A 1 V_p – V_p sinusoidal wave is drawn as shown:

Given,

f_s = Sampling frequency = 25 kHz,

So, T_s = 1/f_s = 40 μsec.,

f_t is a harmonic of f_s,i.e.

f_t = 40 f_s.

The following observations are made:
- If sampling starts exactly at “0” sec, then the output is only 0V.
- If sampling starts exactly at 0.25 μsec, then the output is 0.5 V DC value only
- If sampling starts at 0.75 μsec then the output will be -0.5 V DC value only
So, we conclude that whatever be the sampling start time, the output will be a DC value anywhere between 0.5 and -0.5 V depending on the instance the sampling starts.
Question 12
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For a binary half subtractor having two input A and B, the correct set of logical expressions for the outputs D = (A - B) and X (borrow) are

A

B

C

D

Solution
Question 13
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What type of logic circuit is represented by the figure shown below?

A
XOR

B
AND

C
XAND

D
XNOR

Solution

After solving the circuit we get (A’B’)+AB as output, which is XNOR operation. Thus, it will produce 1 when inputs are even number of 1s or all 0s, and produce 0 when input is odd number of 1s.
Question 14
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The building block shown in fig. is a active high output decoder.

The output X is

A
AB + BC + CA

B
A + B + C

C
ABC

D
None of the above

Solution
Question 15
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The building block shown in fig. is a active high output decoder.

The output Y is

A
A + B

B
B + C

C
C + A

D
None of the above

Solution
Question 16
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A logic circuit consist of two 2 x 4 decoder as shown in fig.

A
0

B
z

C

D
1

Solution
Question 17
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Number of 2 × 1 Multiplexers are required to implement 64 × 1 Multiplexers

A
60

B
61

C
62

D
63

Solution

A 64 × 1 multiplexer has 64 inputs so if we use 2 × 1 multiplexers 32 are needed in the first stage for 64 inputs, the output of these 32 multiplexers are connected to inputs of 16 multiplexers in the second stage.

Similarly, in third stage, 8 (2 × 1) multiplexers are used, in fourth stage 4 are used and finally 2 (2 × 1) multiplexers in the fifth stage, 1 in the sixth stage.

Total 2 × 1 multiplexers needed are 32 + 16 + 8 + 4 + 2 + 1 = 63
Question 18
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The network shown in fig. implements

A
NOR gate

B
NAND gate

C
XOR gate

D
XNOR gate

Solution
Question 19
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The MUX shown in fig. P4.2.31 is 4 * 1 multiplexer. The output Z is

A
ABC

B

C

D

Solution

Correct Answer :- c

Explanation : Z = (bar AB)C + (bar A)B + (bar B)A + AB

= (bar A)[(barB)C + B) + A[(bar B) + B]

= (bar A)[(B + C)] + A

= A + B + C
Question 20
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The MUX shown in fig. is a 4 x 1 multiplexer. The output Z is

A

B

C

D

Solution
Question 21
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A

B

C

D

Solution

The output from the upper first level multiplexer is f_a and from the lower first level multiplexer is f_b
Question 22
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For the logic circuit shown in fig.the output Y is

A

B

C

D

Solution
Question 23
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The logic function F(A, B, C) = Σm(1, 3, 5, 6) can be implemented using

A
One 4 x 1 MUX

B
One 4 x 1 MUX and an OR gate

C
One 4x1 MUX and a AND gate

D
One 4 x 1 MUX and a NOT gate

Solution

Given function,

has three variables. Hence, it can be implemented using a multiplexer ( 4 x 1 M U X) with two select inputs and four data inputs.

The implementation table is shown below:

Now, the given three variable functions can be implemented using 4-to-1 multiplexer as shown below:

Hence, for implementation of given function we require one 4 x 1 MUX and a NOT gate
Question 24
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In a binary adder with two inputs X and Y, the correct set of logical expression for the output S (sum) and C (carry) are respectively

A

B

C

D

Solution
Question 25
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A certain multiplexer can switch one of 32 data inputs to its output. The number of control inputs in this multiplexer

A
32

B
16

C
5

D
8

Solution

No. of input lines = 2^m (where, m = No. of select/ control inputs) or, 32 = 2^m or m = 5.