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Digital Electro...

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  • Question 1
    2 / -0.33

    An 8 –bit D/A converter has step size of 20 mV. The full-scale output and the resolution will be nearly

  • Question 2
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    Match the Boolean expression with its minimal realization

     

    Boolean expression

     

    Minimal realization

    P

    X̅ Y̅ Z̅ + X̅ Y Z̅ + X̅ Y Z

    K

    X (Y + Z)

    Q

    X Y Z + X Y̅ Z + X Y Z̅

    L

    X̅ (Y + Z̅)

    R

    X Y + X Y Z + X Y Z̅ + X̅ Y Z

    M

    Z

    S

    X̅ Y̅ Z + X̅ Y Z + X Y̅ Z + X Y Z

    N

    Y (X + Z)

  • Question 3
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    In the truth table of an N-input OR gate, in the column for the output of the gate,

  • Question 4
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  • Question 5
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    The simplified version of the logic circuit shown below consists of

  • Question 6
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    The circuit shown in figure is a ECL OR-AND- INVERTER circuit. The output Z is

  • Question 7
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    A switching function of four variable, f (w, x y, z) is to equal the product of two other function f1 and f2, of the same variable f = f1f2. The function f and f1 are as follows :

    f = ∑m(4,7,15)

    f = ∑m(0,1,2, 3, 4,7, 8,9,10,11,15)

    The number of full specified function, that will satisfy the given condition, is

  • Question 8
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    A four-variable switching function has minterms m6 and m9. If the literals in these minterms are complemented, the corresponding minterm numbers are

  • Question 9
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    The minimum function that can detect a “divisible by 3’’ 8421 BCD code digit (representation D8 D4 D2 D1) is given by

  • Question 10
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  • Question 11
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    If f(t) is 1 MHz sinusoid with 1 Vp-p and sampling frequency fs is 25 kHz, the output:

  • Question 12
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    For a binary half subtractor having two input A and B, the correct set of logical expressions for the outputs D = (A - B) and X (borrow) are

  • Question 13
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    What type of logic circuit is represented by the figure shown below?

  • Question 14
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    The building block shown in fig. is a active high output decoder.

    The output X is

  • Question 15
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    The building block shown in fig. is a active high output decoder.

    The output Y is

  • Question 16
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    A logic circuit consist of two 2 x 4 decoder as shown in fig.

  • Question 17
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    Number of 2 × 1 Multiplexers are required to implement 64 × 1 Multiplexers

  • Question 18
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    The network shown in fig. implements

  • Question 19
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    The MUX shown in fig. P4.2.31 is 4 * 1 multiplexer. The output Z is

  • Question 20
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    The MUX shown in fig. is a 4 x 1 multiplexer. The output Z is

  • Question 21
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  • Question 22
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    For the logic circuit shown in fig.the output Y is

  • Question 23
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    The logic function F(A, B, C) = Σm(1, 3, 5, 6) can be implemented using

  • Question 24
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    In a binary adder with two inputs X and Y, the correct set of logical expression for the output S (sum) and C (carry) are respectively

  • Question 25
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    A certain multiplexer can switch one of 32 data inputs to its output. The number of control inputs in this multiplexer

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