Digital Electronics Test 3

Result

Digital Electronics Test 3

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Question 1
1 / -0

D input of a clocked D-flip-flop receives and input A ⊕ Q_n where A is an external logic input and Q_n is the output of the n^th D-FF before the clock appears. The circuit works as

A
EXOR gate

B
T-FF

C
D-FF

D
JK-FF

Solution

Characteristic equation of a D flip flop is, Q (n + 1) = D
Characteristic equation of a T flip flop is, Q (n + 1) = T ⊕ Qn
The input of the D flip flop = A ⊕ Q_n
The output of the D flip flop will be, Q (n + 1) = A ⊕ Q_n
It represents, the characteristic equation of T flip flop.
Question 2
1 / -0

The clock frequency of 12 MHz is applied to a cascaded counter of modulus-4 counters, modulus-5 counters and modulus-6 counters.

A
The overall modulus of the cascaded counter is 60

B
The lowest output frequency of the cascaded counter is 100 kHz

C
The overall modulus of the cascaded counter is 120

D
The lowest output frequency of the cascaded counter is 200 kHz

Solution

The overall modulus of the cascaded counter is the multiplication of the modulus of the individual counters.
Overall modulus (N) = 4 × 5 × 6 = 120
The clock frequency (f_clk) = 12 MHz
The lowest output frequency \(= \frac{{{f_{clk}}}}{N}\)
\(= \frac{{12 \times {{10}^6}}}{{120}} = 100\;kHz\)
Question 3
1 / -0

An X-Y flip-flop whose characteristic table is given below is to be implemented using a J-K flip-flop
X
Y
Q_n+1
0
0
1
0
1
Q_n
1
0
Q̅_n
1
1
0

This can be done using-

A
J = X, K = Y̅

B
J = Y, K = X̅

C
J = X̅, K = Y

D
J = Y̅, K = X

Solution

Concept:
The characteristic equation of a J-K flip flop is given by-
⇒ Q_n+1 = JQ̅_n + K̅Q_n
Calculation:
Let Q_n is the present state and Q_n+1 is the next state of the given X-Y flip-flop.
X
Y
Q_n
Q_n+1
0
0
0
1
0
0
1
1
0
1
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
0

Solving the above using K-map, we get the characteristic equation of X-Y flip-flop is-
Q_n+1 = Y̅Q̅_n + X̅Q_n
Characteristic equation of a J-K flip flop is given by
Q_n+1 = JQ̅_n + K̅Q_n
Comparing, J = Y̅ and K = X