Digital Electronics Test 2

(146)_b + (313)_b-2 = (246)₈

b² + 4b + 6 + 3(b-2)² + (b-2) + 3 = 2× 8² + 4×8 + 6

4b² – 7b + 19 = 166

 4b² – 7b – 147 = 0

4b² – 28b + 21b – 147 = 0

4b(b –  7) + 21(b – 7) = 0

(b – 7).(4b + 21) = 0

∴ b = 7 or b = -21 ÷ 4

Since b cannot be negative or in fraction

∴ b = 7

Alternate Method:

Substitute and check the result

b = 7

(146)₇ + (313)_7-2 = (246)₈

LHS = (146)₇ + (317)_7-2

 (146)₇ = 1 × 7² + 4 ×7¹ + 6 × 7⁰ = 49 + 28 + 6 = (83)₁₀

(313)₅ = 3 × 5² + 1 × 5 + 7× 5⁰ = 75 + 5 + 3 = (83)₁₀

LHS = (83)₁₀ + (83)₁₀ = (166)₁₀  

RHS = (246)₈

= 2 × 8² + 4 ×8¹ + 6 × 8⁰

= 128 + 32 + 6 = (166)₁₀  

The overall modulus of the cascaded counter is the multiplication of the modulus of the individual counters.

Overall modulus (N) = 4 × 5 × 6 = 120

The clock frequency (f_clk) = 12 MHz

The lowest output frequency \(= \frac{{{f_{clk}}}}{N}\) 

\(= \frac{{12 \times {{10}^6}}}{{120}} = 100\;kHz\)

The elevator door will open in the following two cases:

Case I: If the elevator is stopped and is level with the floor and the time has not expired

So we’ll have the representation as:

Elevator is stopped = E

Level with the floor = F

Time has not expired = T̅

So, the given condition is expressed as –

X₁ = SFT̅

Case 2: If the elevator is stopped and is level with the floor and a button is pressed.

Again we have the representation as:

Elevator is stopped = S

Level with the floor = F

Button is pressed = B

So, the given condition is expressed as;

X₂ = SFB

Since the door will open in Case-1 ‘OR’ Case-2.

Therefore, we may express the condition for the elevator door to open as D = X₁ or X₂, i.e.

Concept: 

A decoder with k input lines has 2^k output lines.

Calculation:

The memory is byte-addressable. So 64 KB = 2¹⁶ B.

16 × 2¹⁶ decoders.

So, the number of input lines (p) = 16

Number of output lines (q) = 2^p = 2¹⁶ = 65536

∴ p + q = 16 + 65536 = 65552 

The resolution of a 4-bit counting ADC = 0.5 V

That means the voltage corresponding to each count = 0.5 V

For an input of 5.1 V, the number counts that counter will count

\(= \frac{{5.1}}{{0.5}} = 10.2 \approx 1\) 

Digital output = 1011

Maximum conversion time = (2ⁿ - 1) T_clk

Clock frequency (f) = 0.5 MHz

\({T_{clk}} = \frac{1}{f} = \frac{1}{{0.5\; \times \;{{10}^6}}} = 2\;\mu s\) 

Maximum conversion time = (2⁴ - 1) × 2 μs = 30 μs  

The 4-bit output is b₃ b₂ b₁ b₀

Resolution \( = \frac{{15}}{{{2^4} - 1}} = 1\;V\)

For input V_i = 2V:

Output code word: 0001

For input V_i = 1 V:

Output code word: 0001

For input V_i = 4 V:

Output code word: 0100

For input V_i = 6 V: