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Semiconductor E...

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  • Question 1
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    Find the minimum load resistance which can be used for the zener diode as shown in figure. Given, $$V_Z=10 V, R_Z=0 \Omega,  R=450 \Omega, I_Z(min)=2 mA $$ and $$I_Z(max)=60 mA$$

  • Question 2
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    A NOR gate and a NAND gate are connected as shown in the figure. Two different sets of inputs are given to this setup. In the first case, the inputs to the gates are $$A=0,B=0,C=0$$. In the second case, the inputs are $$A=1,B=0,C=1$$. The output $$D$$ in the first case and second case respectively are:

  • Question 3
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    A zener diode voltage regulator operated in the range $$120-180\  V$$ produces a constant supply of $$110\  V$$ and $$250\  mA$$ to the load. If the maximum current is to be equally shared between the load and zener, then the values of series resistance ($$\displaystyle { R }_{ S }$$) and load resistance ($$\displaystyle { R }_{ L }$$) are:

  • Question 4
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    A 5 V zener diode is used to regulate the voltage across load resistor $$R_L$$ and the input voltage varies in between 10 V to 15 V. The load current also varies from 5 mA to 50 mA. Find the value of series resistance R. 

    Given, $$I_Z(min)=20 mA$$

  • Question 5
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    Find the minimum and maximum load currents for which the zener diode as shown in figure will maintain regulation. Given, $$V_Z=10 V, R_Z=0 \Omega,  R=450 \Omega, I_Z(min)=2 mA $$ and $$I_Z(max)=60 mA$$

  • Question 6
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    Which of the following is NOT true about a zener diode?

  • Question 7
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    Consider an open-circuited p-n junction in thermal equilibrium. Let $$J_{p,drift}$$ and $$J_{p,diff}$$ be the hole drift and diffusion current densities, respectively, and let $$J_{n,drift}$$ and $$J_{n,diff}$$ be the corresponding electron current densities. Of the following equalities, mark false,at all points in the p-n junction structure.

  • Question 8
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    In the circuit diagram given A and B are switches. The logic operation, which the switches can perform, is.....?

  • Question 9
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    When a semiconductor is heated, its resistance.

  • Question 10
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    The waveforms A and B given below are given as input to a NAND gate. Then, its logic output $$y$$ is

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