Digital Electro...

An n-bit DAC is desired to change in 1 mV increments while using a reference voltage of 5 V. The number of bits ‘n’ required for the DAC is _______.

The resolution of a 4-bit counting ADC is 0.5 V. For an analog input of 5.1 V, the digital output of the ADC and the maximum conversion time for 0.5 MHz clock frequency are

Suppose you are asked to design an ADC for a speedometer to calculate the speed of a rotating wheel. The dynamo which converts rotation of the wheel into analog electric voltage can generate 0 V (stationary wheel) to 15 V (wheel rotating at top speed). The smallest change in voltage value that the ADC must be capable of representing, is 0.1 V. If you are using a flash ADC converter, how many comparators can be there inside the chip so that it can be used in the given situation?

The analog output voltage of R-2R ladder network based 6-bit DAC with a reference voltage of 5 and for a digital input of 011100 is

In a dual slope ADC, the reference voltage is 100 mV and the first integration period is set as 50 sec. The input resistor of the integrator is 1 kΩ and the integrating capacitor 0.047 μF. If the input of 120 mV is corrupted by power supply interference at 50 Hz having peat amplitude of 3π mV. The worst-case error introduced by the interference in the reading is

A signal channel signal acquisition system with 0-10 V range consist of a sample and hold circuit with worst case drop rate of 100 μV/ms and 10 bit ADC. The maximum conversion time for the ADC is